Patents by Inventor JEEVA PAUDEL

JEEVA PAUDEL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240394951
    Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a graphics processing unit (GPU). The apparatus may detect an existence of a shader termination construct for at least one graphics shader. The apparatus may also perform a first static analysis for an identification of a set of suitable candidates for a control flow delinearization associated with the shader termination construct. Further, the apparatus may perform a second static analysis for a cost modeling procedure for the set of suitable candidates for the control flow delinearization. The apparatus may also select, based on the cost modeling procedure, a candidate of the set of suitable candidates for the control flow delinearization. The apparatus may also provide an indication of the selected candidate of the set of suitable candidates for the control flow delinearization.
    Type: Application
    Filed: May 24, 2023
    Publication date: November 28, 2024
    Inventors: Jeeva PAUDEL, Chunling HU, Yue TANG
  • Patent number: 11829738
    Abstract: A block frequency of a block in an irreducible loop in computer code is statically determined. The statically determining includes splitting an incoming block mass among multiple loop headers of the irreducible loop to provide an initial mass for the block. A bottom-up traversal and a top-down traversal of a plurality of loops of the computer code including the irreducible loop are iteratively performed to update a mass of the block. The iteratively performing commences with propagating the initial mass of the block to one or more blocks of one or more loops of the plurality of loops and continues with propagating and updating masses of select blocks of the plurality of loops until a predefined point is reached providing a resulting mass for the block. The block frequency of the block is determined using the resulting mass and is to be used in processing associated with the computer code.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: November 28, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeeva Paudel, Shimin Cui
  • Publication number: 20230185551
    Abstract: A block frequency of a block in an irreducible loop in computer code is statically determined. The statically determining includes splitting an incoming block mass among multiple loop headers of the irreducible loop to provide an initial mass for the block. A bottom-up traversal and a top-down traversal of a plurality of loops of the computer code including the irreducible loop are iteratively performed to update a mass of the block. The iteratively performing commences with propagating the initial mass of the block to one or more blocks of one or more loops of the plurality of loops and continues with propagating and updating masses of select blocks of the plurality of loops until a predefined point is reached providing a resulting mass for the block. The block frequency of the block is determined using the resulting mass and is to be used in processing associated with the computer code.
    Type: Application
    Filed: December 10, 2021
    Publication date: June 15, 2023
    Inventors: Jeeva Paudel, Shimin Cui
  • Patent number: 11599079
    Abstract: A static safety analysis for control-flow linearization receives a control flow graph (CFG) and an intermediate representation of a computer program, and identifies, for a given loop, all memory load instructions belonging to one side of a diamond-shape structure in the CFG. For each representation of an address of each memory load instruction identified, determining whether it is used on all other sides of the diamond-shape structure. Responsive to determining each representation of an address of each memory load instruction on the one side of the diamond-shape structure is used on all other sides of the diamond-shape structure, determining whether an immediate predecessor of a top of the diamond-shape structure for the given loop post-dominates a header of the given loop. Responsive to determining the immediate predecessor of the top of the diamond-shape structure for the given loop post-dominates the header of the given loop, affirming safety of linearization.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: March 7, 2023
    Assignee: International Business Machines Corporation
    Inventor: Jeeva Paudel
  • Publication number: 20220308543
    Abstract: A static safety analysis for control-flow linearization receives a control flow graph (CFG) and an intermediate representation of a computer program, and identifies, for a given loop, all memory load instructions belonging to one side of a diamond-shape structure in the CFG. For each representation of an address of each memory load instruction identified, determining whether it is used on all other sides of the diamond-shape structure. Responsive to determining each representation of an address of each memory load instruction on the one side of the diamond-shape structure is used on all other sides of the diamond-shape structure, determining whether an immediate predecessor of a top of the diamond-shape structure for the given loop post-dominates a header of the given loop. Responsive to determining the immediate predecessor of the top of the diamond-shape structure for the given loop post-dominates the header of the given loop, affirming safety of linearization.
    Type: Application
    Filed: March 25, 2021
    Publication date: September 29, 2022
    Inventor: Jeeva Paudel
  • Patent number: 10901713
    Abstract: Optimizing program parameters in multithreaded programming may include: generating, for a program, a plurality of low-level metric functions, each of the low-level metric functions calculating a respective low-level metric of a plurality of low-level metrics; generating one or more high-level metric functions for one or more high-level metrics, each of the one or more high-level metric functions comprising a piecewise-rational function based on one or more of the low-level metric functions; and generate, based on the one or more high level-metric functions, one or more data parameter values and one or more hardware parameter values, one or more program parameter values for executing the program, wherein the one or more program parameter values are configured to optimize the one or more high-level metrics.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: January 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Jeeva Paudel, Alexander Brandt, Marc Moreno Maza, Linxiao Wang
  • Publication number: 20200319864
    Abstract: Optimizing program parameters in multithreaded programming may include: generating, for a program, a plurality of low-level metric functions, each of the low-level metric functions calculating a respective low-level metric of a plurality of low-level metrics; generating one or more high-level metric functions for one or more high-level metrics, each of the one or more high-level metric functions comprising a piecewise-rational function based on one or more of the low-level metric functions; and generate, based on the one or more high level-metric functions, one or more data parameter values and one or more hardware parameter values, one or more program parameter values for executing the program, wherein the one or more program parameter values are configured to optimize the one or more high-level metrics.
    Type: Application
    Filed: April 4, 2019
    Publication date: October 8, 2020
    Inventors: JEEVA PAUDEL, ALEXANDER BRANDT, MARC MORENO MAZA, LINXIAO WANG