Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for optimizing a control flow graph of a representation of source code. A processor may obtain a control flow graph including a set of instruction blocks. The processor may identify a set of inefficient instruction blocks that include a set of redundant instructions. The processor may determine a set of complex inefficient instruction blocks that include non-isomorphic regions that are eligible for a transformation. The processor may perform code motion on a complex control flow region of the control flow graph based on the determined set of complex inefficient instruction blocks. The processor may simplify a control flow of the complex control flow region based on the performed code motion. The processor may fuse a first redundancy portion and a second redundancy portion of the set of redundant instructions based on the simplified control flow.

Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for modifying a representation of source code. The representation of source code may include the source code or a transformed form of the source code (e.g., an intermediate representation (IR)). A processor configured to modify the representation of source code may obtain the representation of the source code. The processor may identify that the representation comprises a first set of decomposable write memory accesses. The processor may calculate a second set of slicing criteria based on the identified first set of decomposable write memory accesses. The processor may generate a plurality of representation slices based on the representation of the source code and the calculated second set of slicing criteria. The processor may output an indicator of the generated plurality of representation slices.

Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a graphics processing unit (GPU). The apparatus may detect an existence of a shader termination construct for at least one graphics shader. The apparatus may also perform a first static analysis for an identification of a set of suitable candidates for a control flow delinearization associated with the shader termination construct. Further, the apparatus may perform a second static analysis for a cost modeling procedure for the set of suitable candidates for the control flow delinearization. The apparatus may also select, based on the cost modeling procedure, a candidate of the set of suitable candidates for the control flow delinearization. The apparatus may also provide an indication of the selected candidate of the set of suitable candidates for the control flow delinearization.

Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a graphics processing unit (GPU). The apparatus may detect an existence of a shader termination construct for at least one graphics shader. The apparatus may also perform a first static analysis for an identification of a set of suitable candidates for a control flow delinearization associated with the shader termination construct. Further, the apparatus may perform a second static analysis for a cost modeling procedure for the set of suitable candidates for the control flow delinearization. The apparatus may also select, based on the cost modeling procedure, a candidate of the set of suitable candidates for the control flow delinearization. The apparatus may also provide an indication of the selected candidate of the set of suitable candidates for the control flow delinearization.

Abstract: A block frequency of a block in an irreducible loop in computer code is statically determined. The statically determining includes splitting an incoming block mass among multiple loop headers of the irreducible loop to provide an initial mass for the block. A bottom-up traversal and a top-down traversal of a plurality of loops of the computer code including the irreducible loop are iteratively performed to update a mass of the block. The iteratively performing commences with propagating the initial mass of the block to one or more blocks of one or more loops of the plurality of loops and continues with propagating and updating masses of select blocks of the plurality of loops until a predefined point is reached providing a resulting mass for the block. The block frequency of the block is determined using the resulting mass and is to be used in processing associated with the computer code.

Abstract: A block frequency of a block in an irreducible loop in computer code is statically determined. The statically determining includes splitting an incoming block mass among multiple loop headers of the irreducible loop to provide an initial mass for the block. A bottom-up traversal and a top-down traversal of a plurality of loops of the computer code including the irreducible loop are iteratively performed to update a mass of the block. The iteratively performing commences with propagating the initial mass of the block to one or more blocks of one or more loops of the plurality of loops and continues with propagating and updating masses of select blocks of the plurality of loops until a predefined point is reached providing a resulting mass for the block. The block frequency of the block is determined using the resulting mass and is to be used in processing associated with the computer code.

Abstract: A static safety analysis for control-flow linearization receives a control flow graph (CFG) and an intermediate representation of a computer program, and identifies, for a given loop, all memory load instructions belonging to one side of a diamond-shape structure in the CFG. For each representation of an address of each memory load instruction identified, determining whether it is used on all other sides of the diamond-shape structure. Responsive to determining each representation of an address of each memory load instruction on the one side of the diamond-shape structure is used on all other sides of the diamond-shape structure, determining whether an immediate predecessor of a top of the diamond-shape structure for the given loop post-dominates a header of the given loop. Responsive to determining the immediate predecessor of the top of the diamond-shape structure for the given loop post-dominates the header of the given loop, affirming safety of linearization.

Abstract: A static safety analysis for control-flow linearization receives a control flow graph (CFG) and an intermediate representation of a computer program, and identifies, for a given loop, all memory load instructions belonging to one side of a diamond-shape structure in the CFG. For each representation of an address of each memory load instruction identified, determining whether it is used on all other sides of the diamond-shape structure. Responsive to determining each representation of an address of each memory load instruction on the one side of the diamond-shape structure is used on all other sides of the diamond-shape structure, determining whether an immediate predecessor of a top of the diamond-shape structure for the given loop post-dominates a header of the given loop. Responsive to determining the immediate predecessor of the top of the diamond-shape structure for the given loop post-dominates the header of the given loop, affirming safety of linearization.

Abstract: Optimizing program parameters in multithreaded programming may include: generating, for a program, a plurality of low-level metric functions, each of the low-level metric functions calculating a respective low-level metric of a plurality of low-level metrics; generating one or more high-level metric functions for one or more high-level metrics, each of the one or more high-level metric functions comprising a piecewise-rational function based on one or more of the low-level metric functions; and generate, based on the one or more high level-metric functions, one or more data parameter values and one or more hardware parameter values, one or more program parameter values for executing the program, wherein the one or more program parameter values are configured to optimize the one or more high-level metrics.

Abstract: Optimizing program parameters in multithreaded programming may include: generating, for a program, a plurality of low-level metric functions, each of the low-level metric functions calculating a respective low-level metric of a plurality of low-level metrics; generating one or more high-level metric functions for one or more high-level metrics, each of the one or more high-level metric functions comprising a piecewise-rational function based on one or more of the low-level metric functions; and generate, based on the one or more high level-metric functions, one or more data parameter values and one or more hardware parameter values, one or more program parameter values for executing the program, wherein the one or more program parameter values are configured to optimize the one or more high-level metrics.