Abstract: Techniques for reducing stress in an integrated circuit wafer are disclosed. A silicon substrate may include multiple integrated circuit chips and multiple scribe regions situated between the one of the multiple integrated circuit chips. A particular scribe region includes a plurality of layers and a stress reduction structure that includes, at a particular layer of the plurality of layers, a material whose coefficient of thermal expansion of materials is greater than a coefficient of thermal expansion of the silicon wafer.

Abstract: Techniques for reducing stress in an integrated circuit wafer are disclosed. A silicon substrate may include multiple integrated circuit chips and multiple scribe regions situated between the one of the multiple integrated circuit chips. A particular scribe region includes a plurality of layers and a stress reduction structure that includes, at a particular layer of the plurality of layers, a material whose coefficient of thermal expansion of materials is greater than a coefficient of thermal expansion of the silicon wafer.

Abstract: A method of fabricating a metal-to-metal antifuse, comprising planarizing an insulating layer and a tungsten plug, forming an antifuse material layer over the insulating layer and the tungsten plug, defining the antifuse material layer, forming a barrier metal layer over the antifuse material layer, defining the barrier metal layer, forming an oxide or tungsten layer over the barrier metal layer, forming a layer of photoresist over the oxide or the tungsten layer, defining the oxide or the tungsten layer, removing the photoresist, forming a first masking layer over the barrier metal layer, defining a shape of the antifuse, removing the first masking layer, forming a metal interconnect layer over the insulating layer, forming a second masking layer over the metal interconnect layer, and removing the second masking layer.

Abstract: A method for forming a metal-to-metal antifuse disposed above and insulated from a semiconductor substrate is disclosed. The method comprises forming a first metal layer disposed above and insulated from the semiconductor substrate; forming a layer of antifuse material over and in electrical contact with the first metal layer; forming a second metal layer over and in electrical contact with the layer of antifuse material; and forming at least one barrier layer comprising a layer of TaN between the layer of antifuse material and one of the first and second metal layers.

Abstract: A metal-to-metal antifuse disposed above and insulated from a semiconductor substrate comprises a first metal layer disposed above and insulated from the semiconductor substrate. A layer of antifuse material is disposed over and in electrical contact with the first metal layer. A second metal layer is disposed over and in electrical contact with the layer of antifuse material. At least one barrier layer comprising a layer of TaN is disposed between the layer of antifuse material and one of the first and second metal layers.