Abstract: A semiconductor device may include a pass transistor on a first surface of the substrate, a pulldown transistor sharing an active region with the pass transistor, a pullup transistor sharing a gate with the pulldown transistor, a wordline connected to a gate of the pass transistor, a bitline connected to a drain of the pass transistor, a first power wiring on a second surface of the substrate and connected to a source of the pulldown transistor, and a second power wiring connected to a source of the pullup transistor. A source of the pass transistor and drains of the pulldown and pullup transistors may be connected through one node. The wordline, the bitline, and the second power wiring may be on the first surface of the substrate. A first portion the first power wiring may extend in a direction parallel to a gate of the pass transistor.

Abstract: The present disclosure relates to semiconductor devices, including a semiconductor device including a backside power delivery network (BSPDN). An example semiconductor device includes a substrate comprising a first surface and a second surface opposite to each other, a first active pattern on the first surface, a first gate structure intersecting the first active pattern, and first and second back wiring patterns disposed on the second surface at a same height from the substrate. The first back wiring pattern comprises a first extension portion and a second extension portion each extending in a first direction, and a connection portion extending in a second direction intersecting the first direction to connect the first extension portion to the second extension portion. The second back wiring pattern is spaced apart from the first extension portion in the second direction, and spaced apart from the connection portion in the first direction.

Abstract: A semiconductor device includes a first lower active pattern and a second lower active pattern, a first upper active pattern and a second upper active pattern, a first gate electrode that overlaps the first lower active pattern and the first upper active pattern, a second gate electrode spaced apart from the first gate electrode, a third gate electrode spaced apart from the first gate electrode, a fourth gate electrode spaced apart from the third gate electrode, a first lower source/drain contact that is electrically connected to the first lower active pattern, a first upper source/drain contact that is electrically connected to the second upper active pattern, a lower shared contact in the lower region, and an upper shared contact in the upper region.

Abstract: A semiconductor device having simplicity in design and improved performance and methods for fabricating the same are provided. The semiconductor device includes a substrate including a frontside and a backside opposite the frontside, an electronic device on the frontside of the substrate, an interlayer insulating layer covering the electronic device, a frontside wiring structure on the interlayer insulating layer, a backside wiring structure on the backside of the substrate, and at least one unit chain connecting the electronic device with the backside wiring structure, the unit chain including a through plug passing through the substrate, a connection contact on the interlayer insulating layer, a first chain plug passing through the interlayer insulating layer to connect the through plug with the connection contact, and a second chain plug passing through the interlayer insulating layer to be connected to the through plug.

Abstract: A semiconductor device having simplicity in design and improved performance and methods for fabricating the same are provided. The semiconductor device includes a substrate including a frontside and a backside opposite the frontside, an electronic device on the frontside of the substrate, an interlayer insulating layer covering the electronic device, a frontside wiring structure on the interlayer insulating layer, a backside wiring structure on the backside of the substrate, and at least one unit chain connecting the electronic device with the backside wiring structure, the unit chain including a through plug passing through the substrate, a connection contact on the interlayer insulating layer, a first chain plug passing through the interlayer insulating layer to connect the through plug with the connection contact, and a second chain plug passing through the interlayer insulating layer to be connected to the through plug.

Abstract: A semiconductor device includes a substrate having first and second surfaces, first to third conductive line structures disposed on the first surface, extending in a first direction, and spaced apart from each other in a second direction, and a SRAM unit cell disposed on the first surface, and including first and second inverters connected to each other, a first pass transistor connected to the first inverter, a second pass transistor connected to the second inverter, a first gate electrode included in the first inverter, and a second gate electrode included in the first pass transistor, the first inverter and the first pass transistor are disposed between the first and third conductive line structures, the second inverter and the second pass transistor are disposed between the second and third conductive line structures, and the first and second gate electrodes are disposed between the first and third conductive line structures.

Abstract: Disclosed therein is a flooring, which can secure environment-friendliness by forming a surface layer laminated on an upper face of a base layer using PLA (Poly Lactic Acid) resin instead of wood, easily provide a handcraft surface texture by applying a curved pattern onto the surface of the surface layer using embossing rollers at the time that the surface layer is manufactured, and prevent compression, scratches, discoloration, and so on in comparison with woods. The flooring constructed on a floor of a building includes: a base layer made from one of an MDF, an HDF, and a plywood; and a surface layer having a reinforced layer, a printed layer, and a transparent layer which are laminated on an upper face of the base layer in order, at least one of the layers being made of PLA (Poly Lactic Acid) resin. A curved pattern is formed on an upper face of the surface layer.

Abstract: The present invention relates to a flooring material including a PLA surface layer having a wood pattern. The flooring material includes a surface layer including at least one layer containing a PLA resin, a plywood layer including a veneer disposed on the undersurface of the surface layer, and a synthetic resin layer disposed on the undersurface of the plywood layer. The flooring material is cut in a tongue & groove shape.