Patents by Inventor Jeff A. Levin
Jeff A. Levin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8779824Abstract: Clock signals are distributed on a chip by applying an oscillating magnetic field to the chip. Local clock generation circuits including magnetic field sensors are distributed around the chip and are coupled to local clocked circuitry on the chip. The magnetic field sensors may include clock magnetic tunnel junctions (MTJs) in which a magnetic orientation of the free layer is free to rotate in the free layer plane in response to the applied magnetic field. The MTJ resistance alternates between a high resistance value and a low resistance value as the free layer magnetization rotates. Clock generation circuitry coupled to the clock MTJs senses voltage oscillations caused by the alternating resistance of the clock MTJs. The clock generation circuitry includes amplifiers, which convert the sensed voltage into local clock signals.Type: GrantFiled: December 17, 2012Date of Patent: July 15, 2014Assignee: QUALCOMM IncorporatedInventors: Wenqing Wu, Kendrick H. Yuen, David W. Hansquine, Robert P. Gilmore, Jeff A. Levin
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Publication number: 20140167831Abstract: Clock signals are distributed on a chip by applying an oscillating magnetic field to the chip. Local clock generation circuits including magnetic field sensors are distributed around the chip and are coupled to local clocked circuitry on the chip. The magnetic field sensors may include clock magnetic tunnel junctions (MTJs) in which a magnetic orientation of the free layer is free to rotate in the free layer plane in response to the applied magnetic field. The MTJ resistance alternates between a high resistance value and a low resistance value as the free layer magnetization rotates. Clock generation circuitry coupled to the clock MTJs senses voltage oscillations caused by the alternating resistance of the clock MTJs. The clock generation circuitry includes amplifiers, which convert the sensed voltage into local clock signals.Type: ApplicationFiled: December 17, 2012Publication date: June 19, 2014Applicant: QUALCOMM IncorporatedInventors: Wenqing Wu, Kendrick H. Yuen, David W. Hansquine, Robert P. Gilmore, Jeff A. Levin
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Patent number: 8320373Abstract: A packet-based processing system suitable for various applications, such as for a base station or a terminal in a wireless communication system, is described. The packet-based processing system may include multiple processing modules and at least one transport module. The processing modules may send packets to one another via a common packet interface and may operate asynchronously. The transport module(s) may forward the packets sent by the processing modules and may operate asynchronously with respect to the processing modules. Each processing module may include a network interface, at least one buffer, a packet parser, a packet builder, and at least one processing unit. Each processing module may support at least one service. Each packet may include a header and a payload. The header may include a source service address for a source service sending the packet and a destination service address for a recipient service receiving the packet.Type: GrantFiled: August 19, 2008Date of Patent: November 27, 2012Assignee: QUALCOMM IncorporatedInventors: Mehraban Iraninejad, Jeff Levin, Michael-David N. Canoy, Michael Alexander Howard, Noam A. Ziv, Rohan Sudhakar Salvi
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Patent number: 7593582Abstract: Apparatus, systems and methods for using the selection of an appropriate parameter at decompression are disclosed. In particular, when adaptive block size discrete cosine transform compression is used to compress data, different combinations of sub-blocks can be generated. To decompress the different combinations of sub-blocks, the appropriate parameter is selected based on block size assignment information and the address of data in the data block.Type: GrantFiled: May 22, 2007Date of Patent: September 22, 2009Assignee: QUALCOMM IncorporatedInventors: Senthil Govindaswamy, Judith LaRocca, Jeff Levin
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Publication number: 20090080429Abstract: A packet-based processing system suitable for various applications, such as for a base station or a terminal in a wireless communication system, is described. The packet-based processing system may include multiple processing modules and at least one transport module. The processing modules may send packets to one another via a common packet interface and may operate asynchronously. The transport module(s) may forward the packets sent by the processing modules and may operate asynchronously with respect to the processing modules. Each processing module may include a network interface, at least one buffer, a packet parser, a packet builder, and at least one processing unit. Each processing module may support at least one service. Each packet may include a header and a payload. The header may include a source service address for a source service sending the packet and a destination service address for a recipient service receiving the packet.Type: ApplicationFiled: August 19, 2008Publication date: March 26, 2009Applicant: QUALCOMM IncorporatedInventors: Mehraban Iraninejad, Jeff Levin, Michael-David N. Canoy, Michael Alexander Howard, Noam A. Ziv, Rohan Sudhakar Salvi
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Patent number: 7388993Abstract: Apparatus and method for selecting an appropriate parameter at decompression are disclosed. In particular, when adaptive block size discrete cosine transform compression is used to compress data, different combinations of sub-blocks can be generated. To decompress the different combinations of sub-blocks, the appropriate parameter is selected based on block size assignment information and the address of data in the data block.Type: GrantFiled: October 17, 2005Date of Patent: June 17, 2008Assignee: QUALCOMM IncorporatedInventors: Senthil Govindaswamy, Judith LaRocca, Jeff Levin
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Publication number: 20070248274Abstract: Apparatus, systems and methods for using the selection of an appropriate parameter at decompression are disclosed. In particular, when adaptive block size discrete cosine transform compression is used to compress data, different combinations of sub-blocks can be generated. To decompress the different combinations of sub-blocks, the appropriate parameter is selected based on block size assignment information and the address of data in the data block.Type: ApplicationFiled: May 22, 2007Publication date: October 25, 2007Applicant: QUALCOMM INCORPORATEDInventors: Senthil Govindaswamy, Judith LaRocca, Jeff Levin
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Publication number: 20060034532Abstract: Apparatus and method for selecting an appropriate parameter at decompression are disclosed. In particular, when adaptive block size discrete cosine transform compression is used to compress data, different combinations of sub-blocks can be generated. To decompress the different combinations of sub-blocks, the appropriate parameter is selected based on block size assignment information and the address of data in the data block.Type: ApplicationFiled: October 17, 2005Publication date: February 16, 2006Inventors: Senthil Govindaswamy, Judith LaRocca, Jeff Levin
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Patent number: 6975773Abstract: Apparatus and method for selecting an appropriate parameter at decompression are disclosed. In particular, when adaptive block size discrete cosine transform compression is used to compress data, different combinations of sub-blocks can be generated. To decompress the different combinations of sub-blocks, the appropriate parameter is selected based on block size assignment information and the address of data in the data block.Type: GrantFiled: July 29, 2003Date of Patent: December 13, 2005Assignee: Qualcomm, IncorporatedInventors: Senthil Govindaswamy, Judith LaRocca, Jeff Levin
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Patent number: 6912070Abstract: An apparatus and method for minimizing the code length of an input address for at least one for variable length encoded data is claimed. A block of variable length encoded data is read. The block of variable length encoded data is then converted into sub-optimall encoded data. The variable length encoded data is defined in having a prefix portion and a suffix portion. The prefix portion of the variable length encoded data is used to signify the look-up table. The suffix portion of the variable length encoded data is used as an input address for the look-up table.Type: GrantFiled: August 8, 2000Date of Patent: June 28, 2005Assignee: Qualcomm, Inc.Inventors: Senthil Govindaswamy, A. Chris Irvine, Jeff Levin