Abstract: An apparatus and method are provided. Generally, an input signal is applied across a main path (through an input network) and across a cancellation path (through a cancellation circuit). The cancellation circuit subtracts a cancellation current from the main path as part of the control mechanism, where the magnitude of the cancellation current is based on a gain control signal (that has been linearized to follow a control voltage).

Abstract: An apparatus and method are provided. Generally, an input signal is applied across a main path (through an input network) and across a cancellation path (through a cancellation circuit). The cancellation circuit subtracts a cancellation current from the main path as part of the control mechanism, where the magnitude of the cancellation current is based on a gain control signal (that has been linearized to follow a control voltage).

Abstract: An apparatus and method are provided. Generally, an input signal is applied across a main path (through an input network) and across a cancellation path (through a cancellation circuit). The cancellation circuit subtracts a cancellation current from the main path as part of the control mechanism, where the magnitude of the cancellation current is based on a gain control signal (that has been linearized to follow a control voltage).

Abstract: A path configuration for a power switch and driver can introduce independent parasitic inductance coupled to the power switch to slow a switching speed of the switch and reduce voltage spikes on the switch during switching events. The path for low side supply of the drive to the negative DC voltage reference is separate from the path of the power switch to the reference. The resulting reduction in voltage spikes due to the slowed switching time maintains performance in an audio amplifier without modifying a switch command signal to compensate for voltage spikes. The path configuration avoids reliance on specifying higher rated components that increase application costs.

Abstract: A path configuration for a power switch and driver can introduce independent parasitic inductance coupled to the power switch to slow a switching speed of the switch and reduce voltage spikes on the switch during switching events. The path for low side supply of the drive to the negative DC voltage reference is separate from the path of the power switch to the reference. The resulting reduction in voltage spikes due to the slowed switching time maintains performance in an audio amplifier without modifying a switch command signal to compensate for voltage spikes. The path configuration avoids reliance on specifying higher rated components that increase application costs.

Abstract: A system and method is provided for detecting an over-current condition in a power field-effect transistor (FET). In one embodiment, an over-current detection circuit for detecting an over-current condition in a power FET comprises a current generator circuit operative to generate a reference current and a plurality of matched FETs operative to receive the reference current and provide a reference voltage, the matched FETs being matched to each other and to the power FET. The over-current detection circuit also comprises a comparator operative to measure a drain-to-source voltage of the power FET and to provide an output that indicates that the drain-to-source voltage of the power FET has exceeded the reference voltage.

Abstract: A system and method is provided for detecting an over-current condition in a power field-effect transistor (FET). In one embodiment, an over-current detection circuit for detecting an over-current condition in a power FET comprises a current generator circuit operative to generate a reference current and a plurality of matched FETs operative to receive the reference current and provide a reference voltage, the matched FETs being matched to each other and to the power FET. The over-current detection circuit also comprises a comparator operative to measure a drain-to-source voltage of the power FET and to provide an output that indicates that the drain-to-source voltage of the power FET has exceeded the reference voltage.