Patents by Inventor Jeff C. Olsen

Jeff C. Olsen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6857387
    Abstract: An apparatus and method for fabricating an electronic workpiece in which first and second electrodes within a plasma chamber are respectively connected to low frequency and high frequency RF power supplies. At least one capacitor is connected between the first electrode and electrical ground. The one or more capacitors can reduce or eliminate the coupling of high frequency RF power to any plasma outside the region directly between the two electrodes. Consequently, the invention can improve the performance of the plasma process by concentrating more of the RF power in the region between the two electrodes.
    Type: Grant
    Filed: May 3, 2000
    Date of Patent: February 22, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Sheng Sun, Jeff C. Olsen, Sanjay Yadav, Quanyuan Shang, Kam S. Law
  • Publication number: 20020115269
    Abstract: Deposition methods for preparing amorphous silicon based films with controlled resistivity and low stress are described. Such films can be used as the interlayer in FED manufacturing. They can also be used in other electronic devices which require films with controlled resistivity in the range between those of an insulator and of a conductor. The deposition methods described in the present invention employ the method of chemical vapor deposition or plasma-enhanced chemical vapor deposition; other film deposition techniques, such as physical vapor deposition, also may be used. In one embodiment, an amorphous silicon-based film is formed by introducing into a deposition chamber a silicon-based volatile, a conductivity-increasing volatile including one or more components for increasing the conductivity of the amorphous silicon-based film, and a conductivity-decreasing volatile including one or more components for decreasing the conductivity of the amorphous silicon-based film.
    Type: Application
    Filed: November 2, 2001
    Publication date: August 22, 2002
    Applicant: Applied Materials, Inc.
    Inventors: William R. Harshbarger, Takako Takehara, Jeff C. Olsen, Regina Qiu, Yvonne LeGrice, Guofu J. Feng, Robert M. Robertson, Kam Law
  • Patent number: 6352910
    Abstract: Deposition methods for preparing amorphous silicon based films with controlled resistivity and low stress are described. Such films can be used as the interlayer in FED manufacturing. They can also be used in other electronic devices which require films with controlled resistivity in the range between those of an insulator and of a conductor. The deposition methods described in the present invention employ the method of chemical vapor deposition or plasma-enhanced chemical vapor deposition; other film deposition techniques, such as physical vapor deposition, also may be used. In one embodiment, an amorphous silicon-based film is formed by introducing into a deposition chamber a silicon-based volatile, a conductivity-increasing volatile including one or more components for increasing the conductivity of the amorphous silicon-based film, and a conductivity-decreasing volatile including one or more components for decreasing the conductivity of the amorphous silicon-based film.
    Type: Grant
    Filed: February 12, 1999
    Date of Patent: March 5, 2002
    Assignee: Applied Komatsu Technology, Inc.
    Inventors: William R. Harshbarger, Takako Takehara, Jeff C. Olsen, Regina Qiu, Yvonne LeGrice, Guofu J. Feng, Robert M. Robertson, Kam Law