Patents by Inventor Jeff Charles Morriss

Jeff Charles Morriss has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5909556
    Abstract: Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical bus assembly for conducting data communication transactions between bus agents interconnected to the hierarchical bus assembly. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic of the serial bus elements implement a number of elemental packets and a number of transaction protocols, employing a master/slave model of transaction flow control. Data communication transactions are conducted using the elemental packets and in accordance to the transaction protocols. In some embodiments, these circuitry and complementary logic of the serial bus elements are also used to conduct connection management transactions between the serial bus elements.
    Type: Grant
    Filed: December 1, 1997
    Date of Patent: June 1, 1999
    Assignee: Intel Corporation
    Inventors: Jeff Charles Morriss, Shaun Knoll, Puthiya Kottal Nizar, Richard M. Haslam, Ajay V. Bhatt, Sudarshan Bala Cadambi
  • Patent number: 5742847
    Abstract: Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical serial bus assembly for the bus controller to dynamically generate and maintain a frame based polling schedule for polling the functions of the bus agents connected to the serial bus assembly and the serial bus elements themselves. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic of the serial bus elements support gathering of various critical operating characteristics by the bus controller. The circuitry and logic provided to the bus controller in turn generate the frame based polling schedule in accordance to these gathered critical operating characteristics, guaranteeing latencies and bandwidths to the isochronous functions of the isochronous peripherals.
    Type: Grant
    Filed: October 31, 1994
    Date of Patent: April 21, 1998
    Assignee: Intel Corporation
    Inventors: Shaun Knoll, Jeff Charles Morriss, Ajay V. Bhatt, Puthiya Kottal Nizar, Richard M. Haslam, Sudarshan Bala Cadambi
  • Patent number: 5694555
    Abstract: Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical bus assembly for conducting data communication transactions between bus agents interconnected to the hierarchical bus assembly. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic of the serial bus elements implement a number of elemental packets and a number of transaction protocols, employing a master/slave model of transaction flow control. Data communication transactions are conducted using the elemental packets and in accordance to the transaction protocols. In some embodiments, these circuitry and complementary logic of the serial bus elements are also used to conduct connection management transactions between the serial bus elements.
    Type: Grant
    Filed: March 19, 1996
    Date of Patent: December 2, 1997
    Assignee: Intel Corporation
    Inventors: Jeff Charles Morriss, Shaun Knoll, Puthiya Kottal Nizar, Richard M. Haslam, Ajay V. Bhatt, Sudarshan Bala Cadambi