Abstract: A universal protocol engine circuit aggregates data of multiple communication ports that may use different communication protocols according to a configurable communication protocol. In a transmitter mode, the universal protocol engine circuit references a slot table defining a sequence of the ports to generate output data from the input data received from the ports, and transmits the output data over a wired or wireless communication link. In a receiver mode, the universal protocol engine circuit references the slot table to parse input data from the communication link into output data for each of the ports. The sequence of ports of the slot table may be configurable according to the speed or other properties of the communication ports.

Abstract: A universal protocol engine circuit aggregates data of multiple communication ports that may use different communication protocols according to a configurable communication protocol. In a transmitter mode, the universal protocol engine circuit references a slot table defining a sequence of the ports to generate output data from the input data received from the ports, and transmits the output data over a wired or wireless communication link. In a receiver mode, the universal protocol engine circuit references the slot table to parse input data from the communication link into output data for each of the ports. The sequence of ports of the slot table may be configurable according to the speed or other properties of the communication ports.

Abstract: A storage server includes various components that monitor and control the data flow therebetween. If an egress (downstream) port becomes congested, that information is propagated upstream to the egress components such as the port manager, the traffic manager processor, and the egress storage processor, which are each configured to control their data flow to prevent dropped data frames. In addition, the egress storage processor can communicate the congestion information to the ingress storage processor, which further propagates the congestion information to the ingress components such as the traffic manager processor and the port manager processor. The ingress port manager processor can then direct the ingress port to stop accepting ingress data for the storage server to process until the congestion has been addressed.

Abstract: One or more circuits that validate data frames are provided. The validation may validate information for a fiber channel header and information for a small computer system interface (SCSI) header. The validation is performed by one or more circuits at wire speed.

Abstract: Techniques for searching a data structure using information in entries found in the data structure are provided. A key is determined for an entry in a data structure and an entry for that key is accessed. It is determined if that entry is the correct entry for the key. If not, information in the entry is used to determine a second entry for the key. It is then determined if the second entry is the correct entry for the key. If not, the process continues as described above until the correct entry is found.

Abstract: A line card for a data packet router interfaces to a high-speed standard data link, and has a first portion interfacing to the router and having a plurality of slower ports, and a second portion having a framer compatible with and coupled to the data link. The framer is coupled through an ingress and an egress data path between the framer and the slower ports, each with separate ingress buffers and egress buffers for each port. An interface control circuit controls data packet transfers between the slower ports and the framer in both directions. In a preferred embodiment a function is used by the control circuit to map packets from the link to the ports, using keys extracted from the incoming packets. For an IP packet the key is the source address, destination address (SA/DA)pair, which constrains packets for same IP conversations to be routed by the same path.

Abstract: A line card for a data packet router interfaces to a high-speed standard data link, and has a first portion interfacing to the router and having a plurality of slower ports, and a second portion having a framer compatible with and coupled to the data link. The framer is coupled through an ingress and an egress data path between the framer and the slower ports, each with separate ingress buffers and egress buffers for each port. An interface control circuit controls data packet transfers between the slower ports and the framer in both directions. In a preferred embodiment a function is used by the control circuit to map packets from the link to the ports, using keys extracted from the incoming packets. For an IP packet the key is the source address, destination address (SA/DA)pair, which constrains packets for same IP conversations to be routed by the same path.

Abstract: A line card for a data packet router interfaces to a high-speed standard data link, and has a first portion interfacing to the router and having a plurality of slower ports, and a second portion having a framer compatible with and coupled to the data link. The framer is coupled through an ingress and an egress data path between the framer and the slower ports, each with separate ingress buffers and egress buffers for each port. An interface control circuit controls data packet transfers between the slower ports and the framer in both directions. In a preferred embodiment a function is used by the control circuit to map packets from the link to the ports, using keys extracted from the incoming packets. For an IP packet the key is the source address, destination address (SA/DA) pair, which constrains packets for same IP conversations to be routed by the same path.