Abstract: The present invention comprises a centrally synchronized distributed time-space-time switch fabric wherein connection memory page (CMP) selection information is communicated to remote devices without having to add any extra hardware to the system. The central processor only needs to communicate to the space switch device, and by writing to certain registers in the space switch the processor can control the CMP selection in each of the time switch devices. By providing the page selection information over the same signals that transfer data, these page selection signals do not have to be routed externally or controlled by the distributed software.

Abstract: A scaleable bandwidth interconnect (SBI) for interconnection of physical layer devices with link layer devices which includes an ADD BUS interface operative to receive data from one of the link layer devices and direct it to one of the physical layer devices and a DROP BUS interface operative to receive data from one of the physical layer devices and direct it to one of the link layer devices. By utilizing buses to access each of the physical layer devices and the link layer devices permits interfacing between a high density of physical layer devices and a high density of link layer devices.

Abstract: The serial scaleable bandwidth interconnect (SBI336S) bus provides a 777.6 MHz point-to-point LVDS serial interface that supports a variety of traffic types including support for Fractional links. 8B/10B coding is used on the serial link to provide codes to transmit additional control information across the serial interface. The SBI336S bus encodes ADD BUS clock master timing from the PHY device to the Link Layer device over the DROP BUS. The SBI336S bus can also provide an in-band communication channel between devices.