Abstract: A small size FET has its drain connected to the gate of a high-side power FET of an N-channel half-bridge circuit and its gate connected to the gate of the low-side power FET of the half-bridge circuit. The source of the small FET is connected to ground. If both the high side and low side power FETs receive gate turn-on signals simultaneously, the protection FET turns on and pulls the gate of the high side FET to ground to turn it off. A layout of the FETs on leadframe segments is disclosed so that the small FET is physically adjacent to the two power FETs such that a very short distance exists between the power FETs and their connection points to the control FET.