Patents by Inventor Jeff Gonion
Jeff Gonion has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250217207Abstract: An apparatus may include a processor circuit that may be configured to execute a translation barrier instruction. To execute the translation barrier instruction, the processor circuit may be configured to prevent, until after the translation barrier instruction completes, address translations for instructions that occur subsequent to the translation barrier instruction in program order. The processor circuit may be further configured to complete the translation barrier instruction based on finishing all address translations for instructions that occur prior to the translation barrier instruction in program order.Type: ApplicationFiled: December 5, 2024Publication date: July 3, 2025Inventor: Jeff Gonion
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Publication number: 20250209160Abstract: An apparatus includes a processor circuit with an execution pipeline circuit configured to execute instructions within an instruction stream, including a first instance of an instruction executable to compute an address to access a data array. The first instance of the instruction may specify a set of operands that includes a pointer to a base address of the data array, an index into the data array, and a size of data elements within the data array. In response to receiving the first instance of the instruction, the execution pipeline circuit may be configured to perform an arithmetic operation that includes a multiplication of the index and the size to generate a result for the address. In response to the arithmetic operation generating an overflow condition, the execution pipeline circuit may be further configured to cause a first corrective action that prevents access to the data array.Type: ApplicationFiled: August 7, 2024Publication date: June 26, 2025Inventors: Pierre Habouzit, Michael D. Snyder, Jeff Gonion
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Patent number: 12321746Abstract: Techniques are disclosed relating to data synchronization barrier operations. A system includes a first processor that may receive a data barrier operation request from a second processor include in the system. Based on receiving that data barrier operation request from the second processor, the first processor may ensure that outstanding load/store operations executed by the first processor that are directed to addresses outside of an exclusion region have been completed. The first processor may respond to the second processor that the data barrier operation request is complete at the first processor, even in the case that one or more load/store operations that are directed to addresses within the exclusion region are outstanding and not complete when the first processor responds that the data barrier operation request is complete.Type: GrantFiled: June 16, 2023Date of Patent: June 3, 2025Assignee: Apple Inc.Inventors: Jeff Gonion, John H. Kelm, James Vash, Pradeep Kanapathipillai, Mridul Agarwal, Gideon N. Levinsky, Richard F. Russo, Christopher M. Tsay
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Publication number: 20250103492Abstract: Techniques are disclosed relating to performing remote cache invalidations. In some embodiments, primary processor circuitry is configured to, based on execution of a remote invalidate instruction (e.g., an ISA-defined instruction), send a cache invalidate command to coprocessor circuitry. The coprocessor circuitry includes coprocessor cache circuitry and cache invalidation control circuitry configured to, in response to the cache invalidate command sent by the primary processor, invalidate one or more cache lines in the coprocessor cache circuitry without executing any instructions on the coprocessor circuitry.Type: ApplicationFiled: February 20, 2024Publication date: March 27, 2025Inventors: Brett S. Feero, Dennis R. Bradford, Gaurav Garg, Jeff Gonion, Bernard J. Semeria, James Vash, Richard F. Russo
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Publication number: 20240346817Abstract: Systems and methods are provided for control of a personal computing device based on user face detection and recognition techniques.Type: ApplicationFiled: June 27, 2024Publication date: October 17, 2024Inventors: Jeff GONION, Duncan Robert KERR
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Patent number: 11941428Abstract: Techniques are disclosed relating to an I/O agent circuit. The I/O agent circuit may include one or more queues and a transaction pipeline. The I/O agent circuit may issue, to the transaction pipeline from a queue of the one or more queues, a transaction of a series of transactions enqueued in a particular order. The I/O agent circuit may generate, at the transaction pipeline, a determination to return the transaction to the queue based on a detection of one or more conditions being satisfied. Based on the determination, the I/O agent circuit may reject, at the transaction pipeline, up to a threshold number of transactions that issued from the queue after the transaction issued. The I/O agent circuit may insert the transaction at a head of the queue such that the transaction is enqueued at the queue sequentially first for the series of transactions according to the particular order.Type: GrantFiled: March 31, 2022Date of Patent: March 26, 2024Assignee: Apple Inc.Inventors: Sagi Lahav, Lital Levy-Rubin, Gaurav Garg, Gerard R. Williams, III, Samer Nassar, Per H. Hammarlund, Harshavardhan Kaushikkar, Srinivasa Rangan Sridharan, Jeff Gonion
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Publication number: 20240070090Abstract: In an embodiment, a system employs encryption on memory addresses generated by a source circuit that generates memory transactions (e.g., a processor such as a central processing unit (CPU), a graphics processing unit (GPU), various embedded processors or microcontrollers; or a peripheral device. The encrypted memory address corresponds to the row that is activated for the memory transaction, instead of the memory address generated by the source circuit.Type: ApplicationFiled: August 21, 2023Publication date: February 29, 2024Inventor: Jeff Gonion
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Publication number: 20230421354Abstract: In an embodiment, a processor includes hardware circuitry which may be used to detect that a return address has been modified since it was generated. In response to detecting the modification, the processor may be configured to signal an exception or otherwise initiate error handling to prevent execution at the modified return address. In an embodiment, the processor may perform a cryptographic signature operation on the return address to generate a signed return address, and the signature may be verified before the address is used as a return target.Type: ApplicationFiled: May 31, 2023Publication date: December 28, 2023Applicant: Apple Inc.Inventors: Yin Zin Mark Lam, Jeff Gonion
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Publication number: 20230333851Abstract: Techniques are disclosed relating to data synchronization barrier operations. A system includes a first processor that may receive a data barrier operation request from a second processor include in the system. Based on receiving that data barrier operation request from the second processor, the first processor may ensure that outstanding load/store operations executed by the first processor that are directed to addresses outside of an exclusion region have been completed. The first processor may respond to the second processor that the data barrier operation request is complete at the first processor, even in the case that one or more load/store operations that are directed to addresses within the exclusion region are outstanding and not complete when the first processor responds that the data barrier operation request is complete.Type: ApplicationFiled: June 16, 2023Publication date: October 19, 2023Inventors: Jeff Gonion, John H. Kelm, James Vash, Pradeep Kanapathipillai, Mridul Agarwal, Gideon N. Levinsky, Richard F. Russo, Christopher M. Tsay
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Publication number: 20230252779Abstract: Systems and methods are provided for control of a personal computing device based on user face detection and recognition techniques.Type: ApplicationFiled: April 19, 2023Publication date: August 10, 2023Inventors: Jeff GONION, Duncan Robert KERR
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Patent number: 11720360Abstract: Techniques are disclosed relating to data synchronization barrier operations. A system includes a first processor that may receive a data barrier operation request from a second processor include in the system. Based on receiving that data barrier operation request from the second processor, the first processor may ensure that outstanding load/store operations executed by the first processor that are directed to addresses outside of an exclusion region have been completed. The first processor may respond to the second processor that the data barrier operation request is complete at the first processor, even in the case that one or more load/store operations that are directed to addresses within the exclusion region are outstanding and not complete when the first processor responds that the data barrier operation request is complete.Type: GrantFiled: September 8, 2021Date of Patent: August 8, 2023Assignee: Apple Inc.Inventors: Jeff Gonion, John H. Kelm, James Vash, Pradeep Kanapathipillai, Mridul Agarwal, Gideon N. Levinsky, Richard F. Russo, Christopher M. Tsay
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Patent number: 11676373Abstract: Systems and methods are provided for control of a personal computing device based on user face detection and recognition techniques.Type: GrantFiled: July 24, 2020Date of Patent: June 13, 2023Assignee: Apple Inc.Inventors: Jeff Gonion, Duncan Robert Kerr
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Publication number: 20230064526Abstract: Techniques are disclosed relating to an I/O agent circuit. The I/O agent circuit may include one or more queues and a transaction pipeline. The I/O agent circuit may issue, to the transaction pipeline from a queue of the one or more queues, a transaction of a series of transactions enqueued in a particular order. The I/O agent circuit may generate, at the transaction pipeline, a determination to return the transaction to the queue based on a detection of one or more conditions being satisfied. Based on the determination, the I/O agent circuit may reject, at the transaction pipeline, up to a threshold number of transactions that issued from the queue after the transaction issued. The I/O agent circuit may insert the transaction at a head of the queue such that the transaction is enqueued at the queue sequentially first for the series of transactions according to the particular order.Type: ApplicationFiled: March 31, 2022Publication date: March 2, 2023Inventors: Sagi Lahav, Lital Levy - Rubin, Gaurav Garg, Gerard R. Williams, III, Samer Nassar, Per H. Hammarlund, Harshavardhan Kaushikkar, Srinivasa Rangan Sridharan, Jeff Gonion
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Publication number: 20230063676Abstract: Techniques are disclosed relating to an I/O agent circuit. The I/O agent circuit may include a transaction pipeline and a pool of counters. The I/O agent circuit may initialize a first counter included in the pool of counters with an initial counter value. The I/O agent circuit may assign the first counter to a specific transaction type. The I/O agent circuit may increment the first counter as a part of allocating a transaction of a transaction type included in a set of transaction types different than the specific transaction type. Based on receiving a transaction request to process a first transaction of the specific transaction type, the I/O agent circuit may bind the first transaction to the first counter. The I/O agent circuit may issue the first transaction to the transaction pipeline based on a counter value stored by the first counter matching the initial counter value.Type: ApplicationFiled: March 31, 2022Publication date: March 2, 2023Inventors: Sagi Lahav, Lital Levy - Rubin, Gaurav Garg, Gerard R. Williams, III, Samer Nassar, Per H. Hammarlund, Harshavardhan Kaushikkar, Srinivasa Rangan Sridharan, Jeff Gonion
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Patent number: 11550716Abstract: Techniques are disclosed relating to an I/O agent circuit of a computer system. The I/O agent circuit may receive, from a peripheral component, a set of transaction requests to perform a set of read transactions that are directed to one or more of a plurality of cache lines. The I/O agent circuit may issue, to a first memory controller circuit configured to manage access to a first one of the plurality of cache lines, a request for exclusive read ownership of the first cache line such that data of the first cache line is not cached outside of the memory and the I/O agent circuit in a valid state. The I/O agent circuit may receive exclusive read ownership of the first cache line, including receiving the data of the first cache line. The I/O agent circuit may then perform the set of read transactions with respect to the data.Type: GrantFiled: January 14, 2022Date of Patent: January 10, 2023Assignee: Apple Inc.Inventors: Gaurav Garg, Sagi Lahav, Lital Levy-Rubin, Gerard Williams, III, Samer Nassar, Per H. Hammarlund, Harshavardhan Kaushikkar, Srinivasa Rangan Sridharan, Jeff Gonion, James Vash
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Publication number: 20220318136Abstract: Techniques are disclosed relating to an I/O agent circuit of a computer system. The I/O agent circuit may receive, from a peripheral component, a set of transaction requests to perform a set of read transactions that are directed to one or more of a plurality of cache lines. The I/O agent circuit may issue, to a first memory controller circuit configured to manage access to a first one of the plurality of cache lines, a request for exclusive read ownership of the first cache line such that data of the first cache line is not cached outside of the memory and the I/O agent circuit in a valid state. The I/O agent circuit may receive exclusive read ownership of the first cache line, including receiving the data of the first cache line. The I/O agent circuit may then perform the set of read transactions with respect to the data.Type: ApplicationFiled: January 14, 2022Publication date: October 6, 2022Inventors: Gaurav Garg, Sagi Lahav, Lital Levy - Rubin, Gerard Williams, III, Samer Nassar, Per H. Hammarlund, Harshavardhan Kaushikkar, Srinivasa Rangan Sridharan, Jeff Gonion, James Vash
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Publication number: 20220083338Abstract: Techniques are disclosed relating to data synchronization barrier operations. A system includes a first processor that may receive a data barrier operation request from a second processor include in the system. Based on receiving that data barrier operation request from the second processor, the first processor may ensure that outstanding load/store operations executed by the first processor that are directed to addresses outside of an exclusion region have been completed. The first processor may respond to the second processor that the data barrier operation request is complete at the first processor, even in the case that one or more load/store operations that are directed to addresses within the exclusion region are outstanding and not complete when the first processor responds that the data barrier operation request is complete.Type: ApplicationFiled: September 8, 2021Publication date: March 17, 2022Inventors: Jeff Gonion, John H. Kelm, James Vash, Pradeep Kanapathipillai, Mridul Agarwal, Gideon N. Levinsky, Richard F. Russo, Christopher M. Tsay
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Publication number: 20200356761Abstract: Systems and methods are provided for control of a personal computing device based on user face detection and recognition techniques.Type: ApplicationFiled: July 24, 2020Publication date: November 12, 2020Inventors: Jeff Gonion, Duncan Robert Kerr
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Patent number: 10726242Abstract: Systems and methods are provided for control of a personal computing device based on user face detection and recognition techniques.Type: GrantFiled: December 28, 2015Date of Patent: July 28, 2020Assignee: APPLE INC.Inventors: Jeff Gonion, Duncan Robert Kerr
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Publication number: 20160148042Abstract: Systems and methods are provided for control of a personal computing device based on user face detection and recognition techniques.Type: ApplicationFiled: December 28, 2015Publication date: May 26, 2016Inventors: Jeff Gonion, Duncan Robert Kerr