Abstract: Techniques are disclosed relating to an I/O agent circuit of a computer system. The I/O agent circuit may receive, from a peripheral component, a set of transaction requests to perform a set of read transactions that are directed to one or more of a plurality of cache lines. The I/O agent circuit may issue, to a first memory controller circuit configured to manage access to a first one of the plurality of cache lines, a request for exclusive read ownership of the first cache line such that data of the first cache line is not cached outside of the memory and the I/O agent circuit in a valid state. The I/O agent circuit may receive exclusive read ownership of the first cache line, including receiving the data of the first cache line. The I/O agent circuit may then perform the set of read transactions with respect to the data.

Abstract: In an embodiment, a system employs encryption on memory addresses generated by a source circuit that generates memory transactions (e.g., a processor such as a central processing unit (CPU), a graphics processing unit (GPU), various embedded processors or microcontrollers; or a peripheral device. The encrypted memory address corresponds to the row that is activated for the memory transaction, instead of the memory address generated by the source circuit.

Abstract: Techniques are disclosed relating to an I/O agent circuit. The I/O agent circuit may include a transaction pipeline and a pool of counters. The I/O agent circuit may initialize a first counter included in the pool of counters with an initial counter value. The I/O agent circuit may assign the first counter to a specific transaction type. The I/O agent circuit may increment the first counter as a part of allocating a transaction of a transaction type included in a set of transaction types different than the specific transaction type. Based on receiving a transaction request to process a first transaction of the specific transaction type, the I/O agent circuit may bind the first transaction to the first counter. The I/O agent circuit may issue the first transaction to the transaction pipeline based on a counter value stored by the first counter matching the initial counter value.

Abstract: A processor circuit is configured to receive, while a current software agent is executing in a current execution mode, an indication of an execution mode transition that attempts to change an execution mode index from a current value indicative of the current execution mode to a new value indicative of a new execution mode. The processor circuit is configured to access, based on the current privilege level, particular execution mode transition information in a storage circuit to determine whether the execution mode transition is allowed. The processor circuit is configured to determine, based on particular execution mode transition information, whether to update the current value indicative of the current execution mode. The processor is further configured to update the current value indicative of the current execution mode based on a determination that the execution mode transition is permitted.

Abstract: Apparatuses, methods, computer programs, and computer-readable storage media are disclosed, wherein an instruction associated with instruction fetch address is fetched and processing performs, when the instruction comprises a request specifying a target memory address, an operation dependent on the target memory address. Registers hold values indicative of a current processing state and a current execution context identifier register holds a current execution context identifier indicative of a current execution context within a current process that caused the instruction to be fetched. Memory security, when the instruction comprises the request specifying the target memory address, determines, based on the instruction fetch address, a current region identifier; determines, based on the current region identifier and the current execution context identifier, a permissions index.

Abstract: A processor circuit may execute a program at a current one of a plurality of privilege levels. The processor circuit may include an LSU circuit and an MMU circuit. The LSU circuit may issue memory access instructions that include load/store unprivileged instructions to be performed based on particular permissions that correspond to an unprivileged level. The MMU circuit may receive, from the LSU circuit, an address associated with a particular load/store unprivileged instruction associated with the program. Code for the particular program may be stored in a particular region of the memory circuit. Based on a determination that the current privilege level is the particular privilege level, the MMU circuit may use particular indices to determine permissions for the particular load/store unprivileged instruction. The particular indices may be specified in one or more registers associated with the particular privilege level.

Abstract: An apparatus is provided in which memory security circuitry responds to a branch by determining whether there is permission for the execution context that executes the branch to branch to the target of the branch and taking an error action in the absence of such permission. Exception handling circuitry responds to an exception by branching to an exception handling routine and disabling circuitry disables the memory security circuitry in response to the exception.

Abstract: A processor circuit may include a mode transition circuit, an exception management circuit, and a plurality of circuits configured to assert respective exception signals. The mode transition circuit may be configured to select a particular one of a plurality of processor modes, corresponding to a respective set of memory access permissions. The exception management circuit may be configured to receive an indication of an assertion of a particular exception signal by a respective one of the plurality of circuits, and then select a vector table of a plurality of vector tables based on a determined processor mode of the plurality of processor modes. The exception management circuit may also be configured to, based on the particular exception signal, determine a vector address within the selected vector table and, based on the determined vector address, retrieve a particular exception handler address from the selected vector table.

Abstract: An apparatus is provided that includes an access control register that stores a configuration value and processing circuitry executes instructions. Execution level circuitry applies execution limits of an active execution level for a functionality. Limitation circuitry applies one or more execution limits of a less privileged execution level than the active execution level for the functionality, without affecting the active execution level, in response to the configuration value being a particular value.

Abstract: Techniques are disclosed relating to access control for threads executed by a computer processor. Processor circuitry may include an execution pipeline, a base register and a limit register. The base register and the limit register may define a range of virtual addresses for a thread executed by the execution pipeline. Control circuitry may access a translation table that stores translation entries that map a virtual address space to a physical address space, wherein a given entry includes a thread-private state indication. for a virtual address provided by the thread at a first permission level, the control circuitry may: determine that the thread-private state indication of a corresponding entry of the translation table is set and in response to the determination, provide a translation of the virtual address only if the virtual address falls within the range of virtual addresses.

Abstract: Apparatuses, methods, computer programs and computer-readable storage media are disclosed. An instruction associated with an instruction fetch address is fetched. In response to the instruction an operation defined by the instruction is conditionally performed. Values indicative of a current processing state of processing are held in registers comprising an execution context identifier register holding an execution context identifier indicative of a current process. A current region identifier is determined based on the instruction fetch address. A permissions index is determined based on the current region identifier and the execution context identifier. The permissions index is used to index into a permissions disabling table to determine a set of permission disables and whether or not the operation is prohibited is determined based on the set of permission disables.

Abstract: A processor circuit that can perform predicated vector operations is disclosed. The processor circuit may compare source and destination register locations as identified in a fetched vector instruction that specifies a predicate vector. The processor circuit may also execute the fetched vector instruction based on the predicate vector to generate an output vector. Based on a result of the comparison of the respective names of source and destination registers, the processor circuit may determine values for inactive elements in the output vector by either zeroing the inactive elements in the output vector prior to writing to the destination register or by masking a write of the inactive elements of the output vector to the destination register.

Abstract: Techniques are disclosed relating to performing remote cache invalidations. In some embodiments, primary processor circuitry is configured to, based on execution of a remote invalidate instruction (e.g., an ISA-defined instruction), send a cache invalidate command to coprocessor circuitry. The coprocessor circuitry includes coprocessor cache circuitry and cache invalidation control circuitry configured to, in response to the cache invalidate command sent by the primary processor, invalidate one or more cache lines in the coprocessor cache circuitry without executing any instructions on the coprocessor circuitry.

Abstract: In an embodiment, a processor includes hardware circuitry which may be used to detect that a return address has been modified since it was generated. In response to detecting the modification, the processor may be configured to signal an exception or otherwise initiate error handling to prevent execution at the modified return address. In an embodiment, the processor may perform a cryptographic signature operation on the return address to generate a signed return address, and the signature may be verified before the address is used as a return target.

Abstract: Systems and methods are provided for control of a personal computing device based on user face detection and recognition techniques.

Abstract: Techniques are disclosed relating to performing remote invalidation of memory access permission information. In some embodiments, primary processor circuitry is configured to, based on execution of a remote permission table invalidate instruction (e.g., an ISA-defined instruction), send a remote invalidate command to secondary processor circuitry. The secondary processor circuitry includes permission circuitry and is configured to, in response to the remote invalidate command sent by the primary processor, invalidate one or more entries in the permission circuitry. In some embodiments, the secondary processor performs the invalidate without executing any instructions on the secondary processor circuitry.

Abstract: Techniques are disclosed relating to performing remote cache invalidations. In some embodiments, primary processor circuitry is configured to, based on execution of a remote invalidate instruction (e.g., an ISA-defined instruction), send a cache invalidate command to coprocessor circuitry. The coprocessor circuitry includes coprocessor cache circuitry and cache invalidation control circuitry configured to, in response to the cache invalidate command sent by the primary processor, invalidate one or more cache lines in the coprocessor cache circuitry without executing any instructions on the coprocessor circuitry.

Abstract: Techniques are disclosed relating to performing remote invalidation of memory access permission information. In some embodiments, primary processor circuitry is configured to, based on execution of a remote permission table invalidate instruction (e.g., an ISA-defined instruction), send a remote invalidate command to secondary processor circuitry. The secondary processor circuitry includes secondary processor permission circuitry and is configured to, in response to the remote invalidate command sent by the primary processor, invalidate one or more entries in the secondary processor permission circuitry. In some embodiments, the secondary processor performs the invalidate without executing any instructions on the secondary processor circuitry.

Abstract: Techniques are disclosed relating to data synchronization barrier operations. A system includes a first processor that may receive a data barrier operation request from a second processor include in the system. Based on receiving that data barrier operation request from the second processor, the first processor may ensure that outstanding load/store operations executed by the first processor that are directed to addresses outside of an exclusion region have been completed. The first processor may respond to the second processor that the data barrier operation request is complete at the first processor, even in the case that one or more load/store operations that are directed to addresses within the exclusion region are outstanding and not complete when the first processor responds that the data barrier operation request is complete.

Abstract: Systems and methods are provided for control of a personal computing device based on user face detection and recognition techniques.