Abstract: A fractional-N phase-lock loop (PLL) with a delay line loop (DLL) having a self-calibrating fractional delay element which controls the PLL feedback signal in such a manner that the delay intervals for the feedback signal are: increased when small fractional divisors (<1/2) causing a lagging phase relationship or large fractional divisors (>1/2) causing a leading phase relationship are sensed; and decreased when small fractional divisors (<1/2) causing a leading phase relationship or large fractional divisors (>1/2) causing a lagging phase relationship are sensed.

Abstract: An input protection structure effectively protects input circuitry from positive-going ESD pulses. The input protection structure includes a transistor having a reduced beta, connected in series with one or more diodes between the input pin and VCC. In one embodiment, the transistor having reduced beta is constructed in the same manner as a fuse device. The structure is formed in an integrated fashion, without the need for metallic interconnections within the structure itself, thereby decreasing impedance while minimizing surface area in the integrated surface.

Abstract: A circuit which provides additional drive current during substantially the entire transition of an output signal from a logical one to a logical zero state, thereby causing the pulldown transistor in the TTL output stage to rapidly turn on, providing increased switching speed between logical one and logical zero output state for a given power consumption. Alternatively, for a given switching speed, power consumption is reduced.