Patents by Inventor Jeff Jianhui Ye

Jeff Jianhui Ye has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for reducing silicide defects in integrated circuits
    Patent number: 7960283
    Abstract: A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: June 14, 2011
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Jeff Jianhui Ye, Huang Liu, Alex K H See, Wei Lu, Hai Cong, Hui Peng Koh, Mei Sheng Zhou, Liang Choo Hsia
  • Method for reducing silicide defects in integrated circuits
    Patent number: 7745320
    Abstract: A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: June 29, 2010
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Jeff Jianhui Ye, Huang Liu, Alex K H See, Wei Lu, Hai Cong, Hui Peng Koh, Mei Sheng Zhou, Liang Choo Hsia