Abstract: A method of reducing impact of variation in latency in data transport between clock domains of a physical layer transceiver having physical coding sublayer circuitry with a first clock in a first clock domain and physical medium attachment circuitry with a second clock in a second clock domain, includes determining, during an initial training of a link, a transmit latency value in a transmit direction from the first clock domain to the second clock domain, determining, during the initial training of the link, separately from determining the transmit latency value, a receive latency value in a receive direction from the second clock domain to the first clock domain, and using the transmit latency value and the receive latency value to account for latency in transfer of data between the first clock domain and the second clock domain following the initial training until a subsequent training.

Abstract: A method is disclosed for indicating a status of a transfer of data from a first device to a second device over a network. In one embodiment, the data includes one or more data frames. Each frame includes a header having one or more bits. The method includes setting a last bit of the one or more bits in the header of a last frame of the one or more data frames to a first value if the status of the transfer of data is good and setting the value of the last bit of the last data frame to a second value if the transfer of data failed. This results in a less congested, more efficient network.

Abstract: A method is disclosed for indicating a status of a transfer of data from a first device to a second device over a network. In one embodiment, the data includes one or more data frames. Each frame includes a header having one or more bits. The method includes setting a last bit of the one or more bits in the header of a last frame of the one or more data frames to a first value if the status of the transfer of data is good and setting the value of the last bit of the last data frame to a second value if the transfer of data failed. This results in a less congested, more efficient network.

Abstract: The present invention is related to the checking of encryption. Embodiments of the present invention are based on the discovery that sufficiently high reliability may be established without checking every encryption block. Instead, embodiments of the present invention provide that data being encrypted may be sampled at certain rate (which may be constant or varying) and only the sampled data may be checked. In general, embodiments of the present inventions are applicable to a fast encryption circuit that may encrypt an entire stream of incoming data into a stream of encrypted data and one or more slower (or slow) encryption circuit and/or one or more slow decryption circuit that operate(s) only on selected samples of the incoming or encrypted data in order to check the encryption of the fast circuit. Thus, encryption can be verified without incurring the costs of exhaustively checking all encrypted data.