Patents by Inventor Jeff McCoskey

Jeff McCoskey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for providing data to multi-function memory
    Patent number: 6829692
    Abstract: Disclosed are a system and method of transmitting data or instructions through a data bus to a memory array associated with a core processing circuit. The memory array may be initially adapted to receive data from the data bus and store the data or instructions received from the data bus. At least a portion of the memory array comprising the stored data or instructions may then be configured as a cache memory of the core processing circuit.
    Type: Grant
    Filed: September 14, 2001
    Date of Patent: December 7, 2004
    Assignee: Intel Corporation
    Inventors: Mark A. Schmisseur, Jeff McCoskey, Timothy J. Jehl
  • Shared memory array
    Patent number: 6782463
    Abstract: Disclosed is a device comprising a core processing circuit coupled to a single memory array which is partitioned into at least a first portion as a cache memory of the core processing circuit, and a second portion as a memory accessible by the one or more data transmission devices through a data bus independently of the core processing circuit.
    Type: Grant
    Filed: September 14, 2001
    Date of Patent: August 24, 2004
    Assignee: Intel Corporation
    Inventors: Mark A. Schmisseur, Jeff McCoskey, Timothy J. Jehl
  • System and method for providing data to multi-function memory
    Publication number: 20030056072
    Abstract: Disclosed are a system and method of transmitting data or instructions through a data bus to a memory array associated with a core processing circuit. The memory array may be initially adapted to receive data from the data bus and store the data or instructions received from the data bus. At least a portion of the memory array comprising the stored data or instructions may then be configured as a cache memory of the core processing circuit.
    Type: Application
    Filed: September 14, 2001
    Publication date: March 20, 2003
    Inventors: Mark A. Schmisseur, Jeff McCoskey, Timothy J. Jehl
  • Shared memory array
    Publication number: 20030056075
    Abstract: Disclosed is a device comprising a core processing circuit coupled to a single memory array which is partitioned into at least a first portion as a cache memory of the core processing circuit, and a second portion as a memory accessible by the one or more data transmission devices through a data bus independently of the core processing circuit.
    Type: Application
    Filed: September 14, 2001
    Publication date: March 20, 2003
    Inventors: Mark A. Schmisseur, Jeff McCoskey, Timothy J. Jehl