Patents by Inventor Jeff R. Wienrich

Jeff R. Wienrich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7665399
    Abstract: A system to imprint patterns on impressionable materials by generating a pressure differential within an imprinting chamber by creating a substantial vacuum in an imprinting area is provided. This system can be used to create conductive traces in a substrate onto which integrated circuit chips and dies can be mounted to create semiconductor packages. A low pressure line evacuates air from a material receiving area of a vessel creating a pressure differential across pistons in the vessel to thereby causing the pistons to press microtools into impressionable material layers. The low pressure line helps the microtools conform to any thickness variations in the imprinted material and prevents air pockets from developing between the microtool and the imprinted material.
    Type: Grant
    Filed: May 6, 2008
    Date of Patent: February 23, 2010
    Assignee: INTEL Corporation
    Inventors: Todd L. Biggs, Jeff R. Wienrich
  • Publication number: 20080202363
    Abstract: A system to imprint patterns on impressionable materials by generating a pressure differential within an imprinting chamber by creating a substantial vacuum in an imprinting area is provided. This system can be used to create conductive traces in a substrate onto which integrated circuit chips and dies can be mounted to create semiconductor packages. A low pressure line evacuates air from a material receiving area of a vessel creating a pressure differential across pistons in the vessel to thereby causing the pistons to press microtools into impressionable material layers. The low pressure line helps the microtools conform to any thickness variations in the imprinted material and prevents air pockets from developing between the microtool and the imprinted material.
    Type: Application
    Filed: May 6, 2008
    Publication date: August 28, 2008
    Applicant: Intel Corporation
    Inventors: Todd L. Biggs, Jeff R. Wienrich
  • Patent number: 7383769
    Abstract: A system to imprint patterns on impressionable materials by generating a pressure differential within an imprinting chamber by creating a substantial vacuum in an imprinting area is provided. This system can be used to create conductive traces in a substrate onto which integrated circuit chips and dies can be mounted to create semiconductor packages. A low pressure line evacuates air from a material receiving area of a vessel creating a pressure differential across pistons in the vessel thereby causing the pistons to press microtools into impressionable material layers. The low pressure line helps the microtools conform to any thickness variations in the imprinted material and prevents air pockets from developing between the microtool and the imprinted material.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: June 10, 2008
    Assignee: Intel Corporation
    Inventors: Todd L. Biggs, Jeff R. Wienrich
  • Patent number: 7304381
    Abstract: In some embodiments, an integrated circuit package includes a substrate and a heat spreader coupled to the substrate by fasteners. Thermal interface material thermally couples the die to the heat spreader. The heat spreader is provided over the die and is attached to the substrate with fasteners rather than a sealant-adhesive. Some examples of suitable fasteners may include rivets, barbed connectors, and gripping clips.
    Type: Grant
    Filed: August 2, 2006
    Date of Patent: December 4, 2007
    Assignee: Intel Corporation
    Inventors: Christopher L. Rumer, Sabina J. Houle, Oswald L. Skeete, Mike T. Reiter, Jeff R. Wienrich
  • Patent number: 7199304
    Abstract: Apparatus and methods are provided to enable circuit configuration of a substrate by the setting of settable bits associated with those circuits. An electrically conductive material is deposited onto selected settable bits which closes the desired circuit between the settable bits. In one embodiment in accordance with the invention, a carrier substrate is provided that comprises settable bits which are used to control a microelectronic package's electrical characteristics. In one embodiment, the settable bits are in the form of sets of spaced-apart bit pads which form an open circuit between a logic circuit and electrical ground (Vss). The open circuit is closed with the application of electrically conductive material that bridges the set of spaced-apart bit pads. The settable bits, therefore, do not require the addition of high profile components such as 0-ohm resisters to form the electrical bridging function between the bit pads of a settable bit.
    Type: Grant
    Filed: September 4, 2002
    Date of Patent: April 3, 2007
    Assignee: Intel Corporation
    Inventors: Jeff R. Wienrich, Joni G. Hansen, Debendra Mallik
  • Patent number: 7162810
    Abstract: A micro tool alignment apparatus and method of use is described herein. The micro tool alignment apparatus coarsely aligns multiple imprinting micro tools to one another and includes a plurality of attachment features to facilitate attachment of the micro tool(s) to the alignment apparatus and to facilitate positioning of the micro tool(s) according to a first and a second degree of freedom. Alignment features associated with the micro tool alignment apparatus further facilitate positioning of the micro tool according to a third degree of freedom.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: January 16, 2007
    Assignee: Intel Corporation
    Inventors: Todd L. Biggs, Jeff R. Wienrich
  • Publication number: 20040238947
    Abstract: In some embodiments, an integrated circuit package includes a substrate and a heat spreader coupled to the substrate by fasteners. Thermal interface material thermally couples the die to the heat spreader. The heat spreader is provided over the die and is attached to the substrate with fasteners rather than a sealant-adhesive. Some examples of suitable fasteners may include rivets, barbed connectors, and gripping clips.
    Type: Application
    Filed: May 28, 2003
    Publication date: December 2, 2004
    Applicant: Intel Corporation
    Inventors: Christopher L. Rumer, Sabina J. Houle, Oswald L. Skeete, Mike T. Reiter, Jeff R. Wienrich
  • Publication number: 20040040741
    Abstract: Apparatus and methods are provided to enable circuit configuration of a substrate by the setting of settable bits associated with those circuits. An electrically conductive material is deposited onto selected settable bits which closes the desired circuit between the settable bits. In one embodiment in accordance with the invention, a carrier substrate is provided that comprises settable bits which are used to control a microelectronic package's electrical characteristics. In one embodiment, the settable bits are in the form of sets of spaced-apart bit pads which form an open circuit between a logic circuit and electrical ground (Vss). The open circuit is closed with the application of electrically conductive material that bridges the set of spaced-apart bit pads. The settable bits, therefore, do not require the addition of high profile components such as 0-ohm resisters to form the electrical bridging function between the bit pads of a settable bit.
    Type: Application
    Filed: September 4, 2002
    Publication date: March 4, 2004
    Inventors: Jeff R. Wienrich, Joni G. Hansen, Debendra Mallik