Abstract: Hierarchically-controlled automatic test pattern generation (ATPG) is provided. One embodiment comprises a method for automatically generating test patterns for testing a device under test. Briefly described, one such method comprises the steps of: receiving a hierarchical model of a device under test, the hierarchical model comprising at least one low-level design component and at least one high-level design component which contains the low-level design component; selecting a fault to be detected in the device under test; and performing an automatic test pattern generation (ATPG) algorithm on the design components based on the hierarchy of the hierarchical model.

Abstract: A method and apparatus for generating test patterns used to test an integrated circuit (IC). The apparatus comprises first logic for determining a subset of transition fault sites on an IC to be tested, second logic that identifies a longest sensitizable path through each transition fault site of the subset of transition fault sites, and third logic that generates a bounded set of test patterns that test the identified longest sensitizable paths through each transition fault site of the subset of transition fault sites. The present invention combines various aspects of transition fault modeling and path delay fault modeling to enable global delay testing of an IC within reasonable amount of time.

Abstract: A system and method for evaluating a device under test (DUT) that utilizes a model of the DUT interfaced to DUT interface logic, which is designed to interface the DUT to automated testing equipment (ATE). By ensuring that the model includes a description of the DUT and of the DUT testing interface, conditions such as connections between ports of the IC (i.e., buddying) that may or may not be interfaced to the ATE may be included in the model to enable precise test pattern sets to be generated using the model. The test pattern sets may be used by a simulator to test the design of an IC or by ATE to test a fabricated IC having the design.

Abstract: A method and apparatus of carrying out a computer assisted analysis function on a hierarchical circuit model. The method is carried out by inputting the hierarchical circuit model, specifying at least one circuit block within the hierarchy as a target of the function on the target block, and simplifying the hierarchical circuit model by deleting circuit blocks not affecting the analysis function, to produce a simplified hierarchical circuit model. A computer assisted analysis function can then be carried out on the simplified hierarchical circuit model.

Abstract: The present invention is generally directed to an improved automatic test pattern generator for generating test patterns that are used by an integrated circuit testing device. In accordance with one aspect of the invention, a method is provided for generating a set of test vectors for testing an integrated circuit, each test vector of the set of test vectors containing a plurality of bits defining test inputs for the integrated circuit. The method includes the steps of defining a list of faults for the integrated circuit, and generating at least one test vector that defines values for those inputs necessary to detect at least one target fault selected from the list of faults, the values comprising only a portion of the bits of the at least one test vector, wherein a remainder of the bits in the at least one test vector are unspecified bit positions. The method further includes the step of setting the values of a plurality of the unspecified bit positions using a non-random filling methodology.

Abstract: Systems and methods for generating test patterns are disclosed herein. One such test pattern generating method comprises receiving a netlist of a device under test (DUT), the netlist comprising regions bounded by control/observe points. At least one of the bounded regions is embedded within another bounded region. The method further comprises generating test patterns for the bounded regions using a sequence starting with the deepest embedded bounded regions.

Abstract: Hierarchically-controlled automatic test pattern generation (ATPG) is provided. One embodiment comprises a method for automatically generating test patterns for testing a device under test. Briefly described, one such method comprises the steps of: receiving a hierarchical model of a device under test, the hierarchical model comprising at least one low-level design component and at least one high-level design component which contains the low-level design component; selecting a fault to be detected in the device under test; and performing an automatic test pattern generation (ATPG) algorithm on the design components based on the hierarchy of the hierarchical model.

Abstract: Boundary scan testing methods that detect manufacturing defects in AC-coupled differential pairs may be based on a selected signal parameter: phase or frequency. The data is encoded by the signal parameter. In one embodiment, the signal parameter is compared to reference parameter data provided by the transmitter. In a second embodiment, the reference parameter data is sent from an external source. All the components on board are synchronized with this external source. In a third embodiment, the reference parameter data is embedded in each AC signal between the transmitter and receiver. Two lines of one differential link are used to send different patterns.

Abstract: Methods for testing tri-state bus drivers of a tri-state bus are provided. One such a method can be summarized by: selecting a tri-state bus to be tested; and performing a tri-state test including at least one of a driver speed test procedure and a driver static test procedure, the driver speed test procedure including at least one of testing the selected tri-state bus for an enable line driver slow-to-turn-on condition and an enable line driver slow-to-turn-off condition, the driver static test procedure including at least one of testing the selected tri-state bus for an enable line driver stuck-on condition and an enable line driver stuck-off condition. Systems and other methods also are provided.

Abstract: Systems and methods are provided to test tri-state bus drivers An embodiment of a system includes a tri-state bus to be tested, and at least one tri-state driver connected to the tri-state bus. Either a pull-up driver test circuitry or a pull-down driver test circuitry is connected to the tri-state bus to be tested, and enable the testing of the tri-state driver. An embodiment of a method for testing tri-state bus drivers comprises: selecting the tri-state bus to be tested and performing a tri-state test on the tri-state bus to be tested; switching off enable signals for all drivers on the tri-state bus, forcing the tri-state bus to a first value; setting all driver data inputs to a second value different than the first value, and determining if the first value remains on the tri-state bus.

Abstract: A system and method for evaluating a device under test (DUT) that utilizes a model of the DUT interfaced to DUT interface logic, which is designed to interface the DUT to automated testing equipment (ATE). By ensuring that the model includes a description of the DUT and of the DUT testing interface, conditions such as connections between ports of the IC (i.e., buddying) that may or may not be interfaced to the ATE may be included in the model to enable precise test pattern sets to be generated using the model. The test pattern sets may be used by a simulator to test the design of an IC or by ATE to test a fabricated IC having the design.

Abstract: Method and apparatus of testing current sinking and sourcing capability of a driver in an IC calls for positioning a charge storage element at an output of the driver and charging it to a known voltage value. A pulse of known duration and voltage level is applied to an input of the driver and a resulting voltage value is measured at the output of the driver. A current flow through the driver is determined to be within testing limits by comparing an expected voltage value against the resulting voltage value. An apparatus for testing current sinking and sourcing capacity of a driver in an IC has the driver with a charge storage element of known or measurable capacitive value at an output of the driver. An input circuit permits application of a test pulse of known duration and data input values to the driver. A receiver accepts an output of the driver for determining a threshold voltage value at the driver output.

Abstract: A preferred integrated circuit (IC) includes a first pad electrically communicating with at least a portion of the IC. The first pad includes a first driver and a first receiver, with the first driver being configured to provide a first pad output signal to a component external to the IC, and the first receiver being configured to receive a first pad input signal from a component external to the IC. The first receiver also is configured to provide, to a component internal to the IC, a first receiver digital output signal in response to the first pad input signal. A first test circuit also is provided that is internal to the IC. The first test circuit is adapted to provide information corresponding to the driver clock-to-q time of the first pad. Systems, methods and computer-readable media also are provided.

Abstract: A test method and apparatus allows simultaneous loading of multiple scan chains via a single common scan-in port (SDI) and a scan clock signal SCAN CLOCK. Data is scanned into one or more scanpaths from a scan data in (SDI) port under the control of a clock signal, either directly or indirectly through a linear feedback shift register (LFSR). Scan-out data output from the scanpaths may be read at the scan data out (SDO) port, either directly or indirectly through a signature register with optional masking functionality.

Abstract: A method and apparatus are provided for determining quality metrics associated with a test pattern used to test an integrated circuit (IC). The delays associated with (1) a longest sensitizable path through the IC that includes the delay fault and (2) an actual path exercised by the test pattern through the IC that includes the delay fault are determined. A difference between the delays is then obtained. The difference is then combined with a difference between a speed at which the test is performed and a design specification operating speed of the IC for the actual path. The sum represents the first quality metric associated with the test pattern for a given fault site. The ratio of the delays of the actual path to the longest sensitizable path represents the second quality metric associated with the test pattern for a given fault site.

Abstract: Systems and methods for testing integrated circuits are provided. One such method comprises: providing a target fault list corresponding to an integrated circuit, the target fault list including at least a first fault and a second fault; measuring a relationship between the first fault and the second fault, the relationship corresponding to which of the first fault and the second fault is more readily detected by automatic test pattern generation; ordering the first fault and the second fault within the target fault list in a manner corresponding to the relationship; and performing automatic test pattern generation based upon an order of the faults of the target fault list. Systems and other methods also are provided.

Abstract: A method and apparatus of carrying out a computer assisted analysis function on a hierarchical circuit model. The method is carried out by inputting the hierarchical circuit model, specifying at least one circuit block within the hierarchy as a target of the function on the target block, and simplifying the hierarchical circuit model by deleting circuit blocks not affecting the analysis function, to produce a simplified hierarchical circuit model. A computer assisted analysis function can then be carried out on the simplified hierarchical circuit model.

Abstract: Improvement in the transmission of Boundary Scan Test mode data may be achieved through the assignment of boundary scan test mode traffic to selected bit patterns that facilitate clock recovery and frame alignment in the serial channel. The encoding of boundary scan test traffic as such may be achieved through either multiplexed transmission to the serializer/deserializer (SERDES) alongside a regular channel encoder or incorporated into the channel encoder.

Abstract: A method and apparatus are provided for determining quality metrics associated with a test pattern used to test an integrated circuit (IC). The delays associated with (1) a longest sensitizable path through the IC that includes the delay fault and (2) an actual path exercised by the test pattern through the IC that includes the delay fault are determined. A difference between the delays is then obtained. The difference is then combined with a difference between a speed at which the test is performed and a design specification operating speed of the IC for the actual path. The sum represents the first quality metric associated with the test pattern for a given fault site. The ratio of the delays of the actual path to the longest sensitizable path represents the second quality metric associated with the test pattern for a given fault site.

Abstract: A method and apparatus for generating test patterns used to test an integrated circuit (IC). The apparatus comprises first logic that determining a subset of transition fault sites on an IC to be tested, second logic that identifies a longest sensitizable path through each transition fault site of the subset of transition fault sites, and third logic that generates a bounded set of test patterns that test the identified longest sensitizable paths through each transition fault site of the subset of transition fault sites. The present invention combines various aspects of transition fault modeling and path delay fault modeling to enable global delay testing of an IC within reasonable amount of time.