Patents by Inventor Jeff Rupley
Jeff Rupley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10303480Abstract: Embodiments herein provide for improved store-to-load-forwarding (STLF) logic and linear aliasing effect reduction logic. In one embodiment, a load instruction to be executed is selected. Whether a first linear address associated with said load instruction matches a linear address of a store instruction of a plurality of store instructions in a queue is determined. Data associated with said store instruction for executing said load instruction is forwarded, in response to determining that the first linear address matches the linear address of the store instruction.Type: GrantFiled: October 30, 2013Date of Patent: May 28, 2019Assignee: Advanced Micro DevicesInventors: David A Kaplan, Daniel Hopper, John M. King, Jeff Rupley
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Patent number: 9836304Abstract: A method and apparatus to utilize a fetching scheme for instructions in a processor to limit the expenditure of power caused by the speculative execution of branch instructions is provided. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. The method includes calculating a cumulative confidence measure based on one or more outstanding conditional branch instructions. The method also includes reducing prefetching operations in response to detecting that the cumulative confidence measure is below a first threshold level.Type: GrantFiled: November 15, 2010Date of Patent: December 5, 2017Assignee: Advanced Micro Devices, Inc.Inventors: Marvin Denman, James Dundas, Bradley Gene Burgess, Jeff Rupley
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Patent number: 9626190Abstract: The present invention provides a method and apparatus for floating-point register caching. One embodiment of the method includes mapping a first set of architected registers defined by a first instruction set to a memory outside of a plurality of physical registers. The plurality of physical registers are configured to map to the first set, a second set of architected registers defined by a second construction set, and a set of rename registers. This embodiment of the method also includes adding the physical registers corresponding to the first set of architected registers to the set of rename registers.Type: GrantFiled: October 7, 2010Date of Patent: April 18, 2017Assignee: Advanced Micro Devices, Inc.Inventor: Jeff Rupley
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Patent number: 9361103Abstract: A method is provided for executing a cacheable store. The method includes determining whether to replay a store instruction to re-acquire one or more cache lines based upon a state of the cache line(s) and an execution phase of the store instruction. The store instruction is replayed in response to determining to replay the store instruction. An apparatus is provided that includes a store queue (SQ) configurable to determine whether to replay a store instruction to re-acquire one or more cache lines based upon a state of the cache line(s) and an execution phase of the store instruction. Computer readable storage devices for adapting a fabrication facility to manufacture the apparatus are provided.Type: GrantFiled: November 2, 2012Date of Patent: June 7, 2016Assignee: Advanced Micro Devices, Inc.Inventors: David A. Kaplan, Jeff Rupley, Tarun Nakra
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Patent number: 9244841Abstract: A processor includes a first cache memory and a bus unit in some embodiments. The bus unit includes a plurality of buffers and is operable to allocate a selected buffer of a plurality of buffers for a fill request associated with a first cache line to be stored in a first cache memory, load fill data from the first cache line into the selected buffer, and transfer the fill data to the first cache memory in parallel with storing eviction data for an evicted cache line from the first cache memory in the selected buffer.Type: GrantFiled: December 31, 2012Date of Patent: January 26, 2016Assignee: Advanced Micro Devices, Inc.Inventors: Jeff Rupley, Tarun Nakra
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Publication number: 20150121010Abstract: Embodiments herein provide for improved store-to-load-forwarding (STLF) logic and linear aliasing effect reduction logic. In one embodiment, a load instruction to be executed is selected. Whether a first linear address associated with said load instruction matches a linear address of a store instruction of a plurality of store instructions in a queue is determined. Data associated with said store instruction for executing said load instruction is forwarded, in response to determining that the first linear address matches the linear address of the store instruction.Type: ApplicationFiled: October 30, 2013Publication date: April 30, 2015Inventors: David A Kaplan, Daniel Hopper, John M. King, Jeff Rupley
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Publication number: 20140310500Abstract: The present application describes embodiments of a method and apparatus including a page cross misalign buffer. Some embodiments of the apparatus include a store queue for a plurality of entries configured to store information associated with store instructions. A respective entry in the store queue can store a first portion of information associated with a page crossing store instruction. Some embodiments of the apparatus also include one or more buffers configured to store a second portion of information associated with the page crossing store instruction.Type: ApplicationFiled: April 11, 2013Publication date: October 16, 2014Applicant: Advanced Micro Devices, Inc.Inventors: David A. Kaplan, Jeff Rupley
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Patent number: 8825988Abstract: The present invention provides a method and apparatus for implementing a matrix algorithm for scheduling instructions. One embodiment of the method includes selecting a first subset of instructions so that each instruction in the first subset is the earliest in program order of instructions associated with a corresponding one of a plurality of sub-matrices of a matrix that has a plurality of matrix entries. Each matrix entry indicates the program order of one pair of instructions that are eligible for execution. This embodiment also includes selecting, from the first subset of instructions, the instruction that is earliest in program order based on matrix entries associated with the first subset of instructions.Type: GrantFiled: November 12, 2010Date of Patent: September 2, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Jeff Rupley, Rajagopalan Desikan
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Publication number: 20140189245Abstract: A processor includes a first cache memory and a bus unit in some embodiments. The bus unit includes a plurality of buffers and is operable to allocate a selected buffer of a plurality of buffers for a fill request associated with a first cache line to be stored in a first cache memory, load fill data from the first cache line into the selected buffer, and transfer the fill data to the first cache memory in parallel with storing eviction data for an evicted cache line from the first cache memory in the selected buffer.Type: ApplicationFiled: December 31, 2012Publication date: July 3, 2014Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Jeff Rupley, Tarun Nakra
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Publication number: 20140129776Abstract: A method is provided for executing a cacheable store. The method includes determining whether to replay a store instruction to re-acquire one or more cache lines based upon a state of the cache line(s) and an execution phase of the store instruction. The store instruction is replayed in response to determining to replay the store instruction. An apparatus is provided that includes a store queue (SQ) configurable to determine whether to replay a store instruction to re-acquire one or more cache lines based upon a state of the cache line(s) and an execution phase of the store instruction. Computer readable storage devices for adapting a fabrication facility to manufacture the apparatus are provided.Type: ApplicationFiled: November 2, 2012Publication date: May 8, 2014Applicant: ADVANCED MICRO DEVICES, INC.Inventors: David A. Kaplan, Jeff Rupley, Tarun Nakra
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Publication number: 20120124589Abstract: The present invention provides a method and apparatus for implementing a matrix algorithm for scheduling instructions. One embodiment of the method includes selecting a first subset of instructions so that each instruction in the first subset is the earliest in program order of instructions associated with a corresponding one of a plurality of sub-matrices of a matrix that has a plurality of matrix entries. Each matrix entry indicates the program order of one pair of instructions that are eligible for execution. This embodiment also includes selecting, from the first subset of instructions, the instruction that is earliest in program order based on matrix entries associated with the first subset of instructions.Type: ApplicationFiled: November 12, 2010Publication date: May 17, 2012Inventors: JEFF RUPLEY, Rajagopalan Desikan
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Publication number: 20120124345Abstract: A method and apparatus to utilize a fetching scheme for instructions in a processor to limit the expenditure of power caused by the speculative execution of branch instructions is provided. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. The method includes calculating a cumulative confidence measure based on one or more outstanding conditional branch instructions. The method also includes reducing prefetching operations in response to detecting that the cumulative confidence measure is below a first threshold level.Type: ApplicationFiled: November 15, 2010Publication date: May 17, 2012Inventors: Marvin Denman, James Dundas, Bradley Gene Burgess, Jeff Rupley
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Publication number: 20120089807Abstract: The present invention provides a method and apparatus for floating-point register caching. One embodiment of the method includes mapping a first set of architected registers defined by a first instruction set to a memory outside of a plurality of physical registers. The plurality of physical registers are configured to map to the first set, a second set of architected registers defined by a second construction set, and a set of rename registers. This embodiment of the method also includes adding the physical registers corresponding to the first set of architected registers to the set of rename registers.Type: ApplicationFiled: October 7, 2010Publication date: April 12, 2012Inventor: Jeff Rupley
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Publication number: 20080244224Abstract: In one embodiment, the present invention includes an apparatus having an instruction selector to select an instruction, where the selector is to store a dependent indicator to indicate a direct dependent consumer instruction of a producer instruction, a decode logic coupled to the instruction selector to receive the dependent indicator when the producer instruction is selected and to generate a wakeup signal for the direct dependent consumer instruction, and wakeup logic to receive the wakeup signal and to indicate that the producer instruction has been selected. Other embodiments are described and claimed.Type: ApplicationFiled: March 29, 2007Publication date: October 2, 2008Inventors: Peter Sassone, Jeff Rupley, Bryan Black