Patents by Inventor Jeff Shields

Jeff Shields has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060103039
    Abstract: A device for contracting a pre-expanded polymer material comprises a base comprising a thermally conductive material. The device further comprises a heat transfer body coupled to the base, where the heat transfer body comprises a thermally conductive material, and where the heat transfer body includes a trough configured to receive and transfer heat to a pre-expanded polymer material disposed in the trough. Through the use of the activating/contacting device, a field technician can utilize a portable oven as a heat source, and avoid the need to use a conventional hot air gun or heat ring. In addition, the activating/contacting device can rapidly contract the heat shrink material over an optical fiber cable and connector portion, e.g., in about 2-20 seconds.
    Type: Application
    Filed: November 15, 2004
    Publication date: May 18, 2006
    Inventors: Jeff Shields, Larry Cox, Edward Lurie
  • Patent number: 6432761
    Abstract: A split-gate p-channel memory cell of an EEPROM, and method of fabricating the cell, are provided. The memory cell includes a memory transistor and select transistor that share a common gate. It further includes two independent and distinct threshold voltage adjusts implanted in different portions of a channel region of a substrate of the memory cell. One of the threshold voltage adjusts is disposed in relation to the memory transistor so as to influence its threshold voltage. The other threshold voltage adjust is disposed in relation to the selected transistor so as to influence its threshold voltage. In the method of fabrication, an n-type of dopant is implanted into the substrate to form the threshold voltage adjust associated with the memory transistor and a p-type of dopant is implanted into the substrate to form the threshold voltage adjust associated with the select transistor.
    Type: Grant
    Filed: October 1, 1999
    Date of Patent: August 13, 2002
    Assignee: Microchip Technology Incorporated
    Inventors: Don Gerber, Jeff Shields, David Suda
  • Patent number: 6265294
    Abstract: A fabrication method reduces the amount of discoloration on interlevel dielectric layers due to anti-reflective coatings (ARC). The invention utilizes a barrier layer, such as, silicon nitride (SiN) that prevents the anti-reflective coating from contacting the interlevel dielectric layer (ILD0). The anti-reflective coating can be silicon oxynitride (SiON) deposited by LPCVD or PECVD.
    Type: Grant
    Filed: August 12, 1999
    Date of Patent: July 24, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Stephen Keetai Park, Guarionex Morales, Bharath Rangarajan, Jeff Shields
  • Patent number: 6133142
    Abstract: Reliable vias are formed by providing an adequate landing area without increasing the size of the underlying feature. Embodiments include forming a lower metal feature with an ARC layer extending beyond the side surfaces of the primary conductive portion serving as an etch stop when forming the through-hole. The overhanging portion provides a suitable landing pad without increasing the size of the underlying feature. Embodiments include ARCs having a thickness ranging from about 1000 .ANG. to about 1300 .ANG. and an overhanging portion extending beyond the side surface of the primary conductive portion up to about 0.05 microns.
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: October 17, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Khanh Tran, Jeff Shields