Patents by Inventor Jeff Shu

Jeff Shu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • INTEGRATED CIRCUIT INCLUDING A STRESSED DIELECTRIC LAYER WITH STABLE STRESS
    Publication number: 20110316085
    Abstract: An integrated circuit is provided having a substrate and a transistor in an active region of the substrate. The substrate also has an isolation region having a dielectric material. In one embodiment, a pre-metal dielectric layer is disposed over the substrate and the transistor. At least one of the isolation region or the pre-metal dielectric layer includes a O3 TEOS oxide having a stress retaining dopant. The O3 TEOS oxide induces a stress in a channel region of the transistor.
    Type: Application
    Filed: September 5, 2011
    Publication date: December 29, 2011
    Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Huang LIU, Jeff SHU, Luona GOH, Wei LU
  • Integrated circuit including a stressed dielectric layer with stable stress
    Patent number: 8013372
    Abstract: A method for fabricating an integrated circuit is provided. The method includes providing a substrate having an active region and an opening in the substrate adjacent to the active region. The opening is filled with a dielectric material so as to provide an isolation region in the substrate. A transistor is also formed in the active region and a pre-metal dielectric layer formed over the substrate and transistor. At least one of the dielectric layer in isolation region or the pre-metal dielectric layer includes a stressed O3 TEOS oxide having a stress retaining dopant, wherein the concentration of the stress retaining dopant is sufficient to retard stress degradation of the O3 TEOS oxide.
    Type: Grant
    Filed: April 4, 2008
    Date of Patent: September 6, 2011
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Huang Liu, Jeff Shu, Luona Goh, Wei Lu
  • INTEGRATED CIRCUIT SYSTEM EMPLOYING A MODIFIED ISOLATION STRUCTURE
    Publication number: 20090325359
    Abstract: An integrated circuit system that includes: providing a substrate; forming a trench within the substrate; forming a liner on a sidewall of the trench; and forming a dielectric material at a trench bottom with a dielectric width dimension that exceeds that of a width dimension of the trench.
    Type: Application
    Filed: June 30, 2008
    Publication date: December 31, 2009
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Huang Liu, Johnny Widodo, Jeff Shu, Luona Goh Loh Nah, Jack Cheng, Wei Lu, Jingze Tian, Xuesong Rao
  • STRESSED DIELECTRIC LAYER WITH STABLE STRESS
    Publication number: 20090250764
    Abstract: An integrated circuit is provided having a substrate and a transistor in an active region of the substrate. The substrate also has an isolation region having a dielectric material. In one embodiment, a pre-metal dielectric layer is disposed over the substrate and the transistor. At least one of the isolation region or the pre-metal dielectric layer includes a O3 TEOS oxide having a stress retaining dopant. The O3 TEOS oxide induces a stress in a channel region of the transistor.
    Type: Application
    Filed: April 4, 2008
    Publication date: October 8, 2009
    Applicant: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Huang LIU, Jeff SHU, Luona GOH, Wei LU