Abstract: A method and system of copying memory from a source processor to a target processor by duplicating memory writes. At least some of the exemplary embodiments may be a method comprising stopping execution of a user program on a target processor (the target processor coupled to a first memory), continuing to execute a duplicate copy of the user program on a source processor (the source processor coupled to a second memory and generating writes to the second memory), duplicating memory writes of the source processor and duplicating writes by input/output adapters to create a stream of duplicate memory writes, and applying the duplicated memory writes to the first memory.

Abstract: A method and system of copying memory from a source processor to a target processor by duplicating memory writes. At least some of the exemplary embodiments may be a method comprising stopping execution of a user program on a target processor (the target processor coupled to a first memory), continuing to execute a duplicate copy of the user program on a source processor (the source processor coupled to a second memory and generating writes to the second memory), duplicating memory writes of the source processor and duplicating writes by input/output adapters to create a stream of duplicate memory writes, and applying the duplicated memory writes to the first memory.

Abstract: A processor interface chip and a maintenance diagnostic chip are provided coupled with two microprocessors designed to be run in tandem. The processor interface chip includes logic for interfacing between the microprocessors and a main memory, logic for pipelining multiple microprocessor requests between the microprocessors and main memory, logic for prefetching data before a microprocessor issues a read request, logic for allowing a boot to occur from code anywhere in physical memory without regard to the microprocessors' fixed memory location for boot code, and logic for intelligently limiting the flow of interrupt information over a processor bus between the microprocessors and the processor interface chip.

Abstract: A processor interface chip and a maintenance diagnostic chip are provided coupled with two microprocessors designed to be run in tandem. The processor interface chip includes logic for interfacing between the microprocessors and a main memory, logic for pipelining multiple microprocessor requests between the microprocessors and main memory, logic for prefetching data before a microprocessor issues a read request, logic for allowing a boot to occur from code anywhere in physical memory without regard to the microprocessors' fixed memory location for boot code, and logic for intelligently limiting the flow of interrupt information over a processor bus between the microprocessors and the processor interface chip.

Abstract: A processor interface chip and a maintenance diagnostic chip are provided coupled with two microprocessors designed to be run in tandem. The processor interface chip includes logic for interfacing between the microprocessors and a main memory, logic for pipelining multiple microprocessor requests between the microprocessors and main memory, logic for prefetching data before a microprocessor issues a read request, logic for allowing a boot to occur from code anywhere in physical memory without regard to the microprocessors' fixed memory location for boot code, and logic for intelligently limiting the flow of interrupt information over a processor bus between the microprocessors and the processor interface chip.

Abstract: A processor interface chip and a maintenance diagnostic chip are provided coupled with two microprocessors designed to be run in tandem. The processor interface chip includes logic for interfacing between the microprocessors and a main memory, logic for pipelining multiple microprocessor requests between the microprocessors and main memory, logic for prefetching data before a microprocessor issues a read request, logic for allowing a boot to occur from code anywhere in physical memory without regard to the microprocessors' fixed memory location for boot code, and logic for intelligently limiting the flow of interrupt information over a processor bus between the microprocessors and the processor interface chip.

Abstract: A processor interface chip and a maintenance diagnostic chip are provided coupled with two microprocessors designed to be run in tandem. The processor interface chip includes logic for interfacing between the microprocessors and a main memory, logic for pipelining multiple microprocessor requests between the microprocessors and main memory, logic for prefetching data before a microprocessor issues a read request, logic for allowing a boot to occur from code anywhere in physical memory without regard to the microprocessors' fixed memory location for boot code, and logic for intelligently limiting the flow of interrupt information over a processor bus between the microprocessors and the processor interface chip.

Abstract: A diagnostic system for diagnosing states of circuit elements is described, wherein scannable circuits can be scanned without disturbing the state of unscannable circuits or violating protocols of busses on which unscannable devices are attached. One unscannable device is a standardized microprocessor. A processor interface circuit is coupled between the microprocessor and scannable processor circuits, via a processor bus, to insulate the scannable processor circuits from the unscannable microprocessor. The processor interface circuit is also scannable, including memory elements which affect the bus, by preventing a scan when the bus is in use. A scan is prevented through the use of a maintenance request signal from a scan controller to the processor interface circuit, and one or more maintenance approval signals from the processor interface circuit to the scan controller.