Abstract: In one embodiment, the present invention includes apparatus that is formed on a single semiconductor die having one or more cores, a memory controller, and a hub coupled to the memory controller. The hub includes multiple fabrics each to communicate with a peripheral controller via a target interface and a master interface according to a first protocol, and where the fabrics are serially coupled via a first plurality of target interfaces in an upstream direction and a second plurality of target interfaces in a downstream direction. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes apparatus that is formed on a single semiconductor die having one or more cores, a memory controller, and a hub coupled to the memory controller. The hub includes multiple fabrics each to communicate with a peripheral controller via a target interface and a master interface according to a first protocol, and where the fabrics are serially coupled via a first plurality of target interfaces in an upstream direction and a second plurality of target interfaces in a downstream direction. Other embodiments are described and claimed.

Abstract: A method and apparatus are provided for a high frequency, low power clock distribution within a very large scale integrated (VLSI) circuit chip. The apparatus for a high frequency, low power clock distribution within a very large scale integrated (VLSI) circuit chip includes a first clock circuit generating a first clock signal. A first level inverter is coupled to the first clock circuit receiving the first clock signal. A clock multiplier is coupled to the first level inverter, generating a multiplied clock signal. A plurality of inverters are coupled to the clock multiplier for driving logic circuits within the VLSI circuit chip at the multiplied clock signal.

Abstract: Methods and apparatus are provided for body control in silicon-on-insulator (SOI) domino circuits. The silicon-on-insulator (SOI) domino circuit includes a clock input and an input transistor stack including a plurality of input transistors. Each of the plurality of input transistors receives a data input. An intermediate precharge node is connected to the input transistor stack. An output inverter is connected to the intermediate precharge node. The output inverter includes a pair of silicon-on-insulator (SOI) transistors. A clocked transistor is connected to a body of at least one of the pair of silicon-on-insulator (SOI) transistors. The clocked transistor predischarges the body of the SOI transistor. Another clocked transistor is connected between ground and a body of an evaluate transistor connected to the input transistor stack. The body of the evaluate transistor is predischarged by the clocked transistor.

Abstract: In brief, methods and apparatus are provided for bipolar elimination in silicon-on-insulator (SOI) domino circuits. Apparatus for bipolar elimination in silcon-on-insulator (SOI) domino circuit includes a domino silicon-on-insulator (SOI) field effect transistor. An input is coupled to the domino silicon-n-insulator (SOI) field effect transistor. A predischarging device is coupled to said domino silicon-on-insulator (SOI) field effect transistor. The predischarging device is activated during a precharge mode of the domino circuit, so that the SOI parasitic bipolar transistor is not activated. A dynamic input circuit couples the input to the domino silicon-on-insulator (SOI) field effect transistor. The output of the dynamic input circuit is low during the precharge mode. The output of the dynamic input circuit corresponds to the input during the evaluate mode. The output of the dynamic input circuit is used to gate the predischarging device.