Patents by Inventor Jeff Van Tran

Jeff Van Tran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for elimination of parasitic bipolar action in logic circuits including complementary oxide semiconductor (CMOS) silicon on insulator (SOI) elements
    Patent number: 6278157
    Abstract: The present invention is an apparatus and method to overcome the unwanted effects of parasitic bipolar discharge in silicon-on-insulator (SOI) field effect transistors (FET) by expanding a stack SOI MOS devices arranged to provide a predetermined logic function. The SOI MOS devices are arranged so as to eliminate electrical connections between certain intermediate nodes of the dynamic logic circuit. Accordingly, eliminating any parasitic bipolar current leakage paths associated with such electrical connections between certain intermediate nodes of said stacked SOI MOS devices of said dynamic circuit.
    Type: Grant
    Filed: January 29, 1999
    Date of Patent: August 21, 2001
    Assignee: International Business Machines Corporation
    Inventors: Jeff Van Tran, Salvatore N. Storino
  • Method for elimination of parasitic bipolar action in silicon on insulator (SOI) dynamic logic circuits
    Patent number: 6271686
    Abstract: The present invention is an apparatus and method to overcome the unwanted effects of parasitic bipolar discharge in silicon-on-insulator (SOI) field effect transistors (FET) by expanding a stack SOI MOS devices arranged to provide a predetermined logic function. The SOI MOS devices are arranged so as to eliminate electrical connections between certain intermediate nodes of the dynamic logic circuit. Accordingly, eliminating any parasitic bipolar current leakage paths associated with such electrical connections between certain intermediate nodes of said stacked SOI MOS devices of said dynamic circuit.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: August 7, 2001
    Assignee: International Business Machines Corporation
    Inventors: Jeff Van Tran, Salvatore N. Storino
  • Method for elimination of parasitic bipolar action in silicon on insulator (SOI) dynamic logic circuits
    Publication number: 20010000950
    Abstract: The present invention is an apparatus and method to overcome the unwanted effects of parasitic bipolar discharge in silicon-on-insulator (SOI) field effect transistors (FET) by expanding a stack SOI MOS devices arranged to provide a predetermined logic function. The SOI MOS devices are arranged so as to eliminate electrical connections between certain intermediate nodes of the dynamic logic circuit. Accordingly, eliminating any parasitic bipolar current leakage paths associated with such electrical connections between certain intermediate nodes of said stacked SOI MOS devices of said dynamic circuit.
    Type: Application
    Filed: December 29, 2000
    Publication date: May 10, 2001
    Applicant: International Business Machines Corporation
    Inventors: Jeff Van Tran, Salvatore N. Storino
  • Method and apparatus for elimination of parasitic bipolar action in logic circuits for history removal under stack contention including complementary oxide semiconductor (CMOS) silicon on insulator (SOI) elements
    Patent number: 6188247
    Abstract: The present invention is an apparatus and method to overcome the unwanted effects of parasitic bipolar discharge in silicon-on-insulator (SOI) field effect transistors (FET) by eliminating the effects the sneak current discharging path by applying a contention free arrangement methodology to realize the dynamic logic circuit. The SOI MOS devices are arranged so as to eliminate the effects of electrical connections between certain intermediate nodes of the dynamic logic circuit. Accordingly, eliminating any parasitic bipolar current leakage paths associated with such electrical connections between certain intermediate nodes of said stacked SOI MOS devices of said dynamic circuit.
    Type: Grant
    Filed: January 29, 1999
    Date of Patent: February 13, 2001
    Assignee: International Business Machines Corporation
    Inventors: Salvatore N. Storino, Jeff Van Tran