Abstract: A system and method for performing tensor transforms on customized digital hardware. The system is comprised of a plurality of computational blocks, a control unit, and memory. The control unit is configured to read the generated source tensor slices for the generated indexes and read from memory the source tensor data and weight data interpolate the tensor slices based on the weights according to a transformation guide. The source tensor data and tensor weights are sent to multiple computational blocks for parallel generation of interpolated output tensor data. The data in memory can be configured so that only one address is needed to read multiple tensor dimensions or a tensor slice. Additionally, the memory can be configured to accept multiple memory addresses in parallel. The computational block output provides a grid-sampled output tensor.

Abstract: A semiconductor device, and a method of its manufacture, are disclosed. The semiconductor device includes a semiconductor die, such as a controller die, mounted on a surface of a substrate. A bridge structure is also mounted to the substrate, with the semiconductor die fitting within a trench formed in a bottom surface of the bridge structure. The bridge structure may be formed from a semiconductor wafer into either a dummy bridge structure functioning as a mechanical spacer layer, or an IC bridge structure functioning as both a mechanical spacer layer and an integrated circuit semiconductor die. Memory die may also be mounted atop the bridge structure.

Abstract: A semiconductor device, and a method of its manufacture, are disclosed. The semiconductor device includes a semiconductor die, such as a controller die, mounted on a surface of a substrate. A bridge structure is also mounted to the substrate, with the semiconductor die fitting within a trench formed in a bottom surface of the bridge structure. The bridge structure may be formed from a semiconductor wafer into either a dummy bridge structure functioning as a mechanical spacer layer, or an IC bridge structure functioning as both a mechanical spacer layer and an integrated circuit semiconductor die. Memory die may also be mounted atop the bridge structure.