Abstract: A static memory cell having no more than three transistors. A static memory cell is formed by providing a semiconductor substrate; forming a buried n-type layer in the substrate, the n-type layer having a first average n-type dopant concentration of at least 1.times.10.sup.16 ions/cm.sup.3 ; forming an n-channel transistor relative to the substrate over the buried n-type layer, the n-channel transistor having a source, a gate, and a drain, the source having a second average n-type dopant concentration of at least 1.times.10.sup.19 ions/cm.sup.3 and the drain having a third average n-type dopant concentration of at least 1.times.10.sup.19 ions/cm.sup.3, and the source having a depth deeper than the drain so as to be closer to the buried n-type layer than the drain; and forming a p-type region in junction with the source to define a tunnel diode between the p-type region and the source.

Abstract: A method of forming CMOS integrated circuitry includes, a) providing a series of field oxide regions and a series of gate lines over a semiconductor substrate, a first gate line being positioned for formation of an NMOS transistor, a second gate line being positioned for formation of a PMOS transistor; b) providing a layer of polysilicon to define a first and second pairs of polysilicon outward projections extending from the semiconductor substrate adjacent the first and second gate lines, respectively; c) masking one of the first or second pair of polysilicon projections while conductively doping the other of the first or second pair with an n-type or a p-type conductivity enhancing dopant impurity, respectively; d) masking the other of the first or second pair of polysilicon projections while conductively doping the one of the first or second pair of polysilicon projections with an n-type or a p-type conductivity enhancing dopant impurity, respectively; e) out-diffusing conductivity enhancing dopant impurit