Patents by Inventor Jefferson Talledo

Jefferson Talledo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10109563
    Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: October 23, 2018
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Rennier Rodriguez, Aiza Marie Agudon, Jefferson Talledo, Moonlord Manalo, Ela Mia Cadag, Rammil Seguido
  • Publication number: 20180286789
    Abstract: The present disclosure is directed to a leadframe package having a side solder ball contact and methods of manufacturing the same. A plurality of solder balls are coupled to recesses in a leadframe before encapsulation and singulation. After singulation, a portion of each solder ball is exposed on sidewalls of the package. This ensures that the sidewalls of the leads are solder wettable, which allows for the formation of stronger joints when the package is coupled to a substrate. This increased adhesion reduces resistance at the joints and also mitigates the effects of expansion of the components in the package such that delamination is less likely to occur. As a result, packages with a side solder ball contact have increased life cycle expectancies.
    Type: Application
    Filed: April 12, 2018
    Publication date: October 4, 2018
    Inventors: Jefferson TALLEDO, Tito MANGAOANG
  • Publication number: 20180204786
    Abstract: The present disclosure is directed to a die having a metallized sidewall and methods of manufacturing the same. A contiguous metal layer is applied to each edge of a backside of a wafer. The wafer is cut at a base of a plurality of channels formed in the backside to create individual die each having a flange that is part of a sidewall of the die and includes a portion that is covered by the metal layer. When an individual die is coupled to a die pad, a semiconductive glue bonds the metal layer on the sidewall and a backside of the die to the die pad, which decreases the risk of delamination along the sides of the die. The flange also prevents the glue from contacting the active side of the die by acting as a barrier against adhesive creep of the glue up the sidewall of the die.
    Type: Application
    Filed: January 18, 2017
    Publication date: July 19, 2018
    Inventors: Rennier RODRIGUEZ, Aiza Marie AGUDON, Jefferson TALLEDO
  • Publication number: 20180197809
    Abstract: A semiconductor device may include a circuit board having an opening, and a frame. The frame may have an IC die pad in the opening, and arms extending outwardly from the IC die pad and coupled to the circuit board. The semiconductor device may include an IC mounted on the IC die pad, bond wires coupling the circuit board with the IC, and encapsulation material surrounding the IC, the bond wires, and the arms.
    Type: Application
    Filed: March 5, 2018
    Publication date: July 12, 2018
    Inventors: Jefferson Talledo, Rammil Seguido
  • Publication number: 20180190576
    Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.
    Type: Application
    Filed: January 5, 2017
    Publication date: July 5, 2018
    Inventors: Rennier Rodriguez, Aiza Marie Agudon, Jefferson Talledo, Moonlord Manalo, Ela Mia Cadag, Rammil Seguido
  • Patent number: 10008472
    Abstract: A method is for making a semiconductor device. The method may include providing a lead frame having a recess, forming a sacrificial material in the recess of the lead frame, and mounting an IC on the lead frame. The method may include encapsulating the IC and the lead frame, removing portions of the lead frame to define lead frame contacts for the IC, and removing the sacrificial material to define for each lead frame contact a solder anchoring tab extending outwardly at a lower region and defining a sidewall recess between opposing portions of the solder anchoring tab and the encapsulation material.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: June 26, 2018
    Assignee: STMICROELECTRONICS, INC.
    Inventor: Jefferson Talledo
  • Publication number: 20180144952
    Abstract: One or more embodiments are directed to semiconductor packages with one or more cantilever pads and methods of making same. In one embodiment a recess is located in a substrate of the package facing the cantilever pad. The cantilever pad includes a conductive pad on which a conductive ball is formed. The cantilever pad is configured to absorb stresses acting on the package.
    Type: Application
    Filed: January 19, 2018
    Publication date: May 24, 2018
    Inventors: Jefferson Talledo, Godfrey Dimayuga
  • Patent number: 9972558
    Abstract: The present disclosure is directed to a leadframe package having a side solder ball contact and methods of manufacturing the same. A plurality of solder balls are coupled to recesses in a leadframe before encapsulation and singulation. After singulation, a portion of each solder ball is exposed on sidewalls of the package. This ensures that the sidewalls of the leads are solder wettable, which allows for the formation of stronger joints when the package is coupled to a substrate. This increased adhesion reduces resistance at the joints and also mitigates the effects of expansion of the components in the package such that delamination is less likely to occur. As a result, packages with a side solder ball contact have increased life cycle expectancies.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: May 15, 2018
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Jefferson Talledo, Tito Mangaoang
  • Publication number: 20180130767
    Abstract: A method is for making a semiconductor device. The method may include providing a lead frame having a recess, forming a sacrificial material in the recess of the lead frame, and mounting an IC on the lead frame. The method may include encapsulating the IC and the lead frame, removing portions of the lead frame to define lead frame contacts for the IC, and removing the sacrificial material to define for each lead frame contact a solder anchoring tab extending outwardly at a lower region and defining a sidewall recess between opposing portions of the solder anchoring tab and the encapsulation material.
    Type: Application
    Filed: January 5, 2018
    Publication date: May 10, 2018
    Inventor: Jefferson Talledo
  • Patent number: 9947636
    Abstract: A method for making a semiconductor device may include bonding a top lead frame component, having recesses, with a bottom lead frame component to form a lead frame, the top and bottom lead frame components each including metal. The method may include mounting an IC on the lead frame, encapsulating the IC and the lead frame, and removing portions of the bottom lead frame component to define contacts for the IC.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: April 17, 2018
    Assignee: STMICROELECTRONICS, INC.
    Inventor: Jefferson Talledo
  • Patent number: 9947612
    Abstract: A semiconductor device may include a circuit board having an opening, and a frame. The frame may have an IC die pad in the opening, and arms extending outwardly from the IC die pad and coupled to the circuit board. The semiconductor device may include an IC mounted on the IC die pad, bond wires coupling the circuit board with the IC, and encapsulation material surrounding the IC, the bond wires, and the arms.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: April 17, 2018
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Jefferson Talledo, Rammil Seguido
  • Publication number: 20180096923
    Abstract: The present disclosure is directed to a semiconductor die on a tapeless leadframe and covered in encapsulant. The semiconductor package includes leads formed from the leadframe and electrically coupled to the semiconductor die, the leads being accessible through electrical contacts embedded in the encapsulant. Openings between the leads and the leadframe are formed from etching recesses from opposing sides of the leadframe. The resulting openings have non-uniform sidewalls. The leadframe is further electrically or thermally coupled to electrical contacts embedded in the encapsulant. The embedded electrical contacts forming a land grid array.
    Type: Application
    Filed: September 30, 2016
    Publication date: April 5, 2018
    Inventor: Jefferson Talledo
  • Publication number: 20180068932
    Abstract: Embodiments of the present disclosure are directed to leadframes having the cantilevered extension that includes an integral support on the end of the lead nearest the die pad. A support integral to the leadframe allows the support to be built to the proper height to support the cantilevered lead in each package and reduces or eliminates the upward, downward, and side to side deflections caused or allowed by supports built-in to the tooling of the manufacturing equipment. Also, by building the support into the leadframe, the leadframes may be pretaped prior to the die attach and wire bonding steps of the manufacturing process.
    Type: Application
    Filed: November 1, 2017
    Publication date: March 8, 2018
    Inventor: Jefferson Talledo
  • Patent number: 9899236
    Abstract: One or more embodiments are directed to semiconductor packages with one or more cantilever pads. In one embodiment a recess is located in a substrate of the package facing the cantilever pad. The cantilever pad includes a conductive pad on which a conductive ball is formed. The cantilever pad is configured to absorb stresses acting on the package.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: February 20, 2018
    Assignee: STMicroelectronics, Inc.
    Inventors: Jefferson Talledo, Godfrey Dimayuga
  • Patent number: 9847281
    Abstract: Embodiments of the present disclosure are directed to leadframes having the cantilevered extension that includes an integral support on the end of the lead nearest the die pad. A support integral to the leadframe allows the support to be built to the proper height to support the cantilevered lead in each package and reduces or eliminates the upward, downward, and side to side deflections caused or allowed by supports built-in to the tooling of the manufacturing equipment. Also, by building the support into the leadframe, the leadframes may be pretaped prior to the die attach and wire bonding steps of the manufacturing process.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: December 19, 2017
    Assignee: STMICROELECTRONICS, INC.
    Inventor: Jefferson Talledo
  • Publication number: 20170358555
    Abstract: One or more embodiments are directed to stacked packages, such as Package-on-Package (PoP) packages, that are stacked on a flexible folded substrate. The stacked packages have compliant corners. In particular, the stacked packages include an adhesive material at the corners between layers of the folded substrate. The adhesive material has a low modulus of elasticity, such as, for example, a modulus of elasticity of silicone adhesive. The low modulus of elasticity of the adhesive material produces compliant corners of the stacked package. The adhesive material fills openings between the folded substrate that are formed around a bottom semiconductor package of the stack package. In that regard, the bottom semiconductor package may have pulled back or recessed corners and the adhesive material fills the openings formed by the recessed corners. The recessed corners may be any size or shape.
    Type: Application
    Filed: June 13, 2016
    Publication date: December 14, 2017
    Inventor: Jefferson Talledo
  • Patent number: 9841341
    Abstract: A surface mounting device has one body of semiconductor material such as an ASIC, and a package surrounding the body. The package has a base region carrying the body, a cap and contact terminals. The base region has a Young's modulus lower than 5 MPa. For forming the device, the body is attached to a supporting frame including contact terminals and a die pad, separated by cavities; bonding wires are soldered to the body and to the contact terminals; an elastic material is molded so as to surround at least in part lateral sides of the body, fill the cavities of the supporting frame and cover the ends of the bonding wires on the contact terminals; and a cap is fixed to the base region. The die pad is then etched away.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: December 12, 2017
    Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS, INC.
    Inventors: Fulvio Vittorio Fontana, Jefferson Talledo
  • Patent number: 9842794
    Abstract: One or more embodiments are directed to semiconductor packages having an integrated heatsink and methods of forming same. In one embodiment, a package includes a plurality of leads that support and enclose periphery portions of the semiconductor die. The leads have first and second, opposing surfaces that form outer surfaces of the package. The first surface of the leads may form a heatsink and the second surface of the leads form lands of the package for coupling to another device, substrate, or board. The package includes encapsulation material that surrounds the semiconductor die and located between upper portions of the leads. The package further includes a back filling material (or insulating material) that is below the semiconductor die and between lower portions of the leads.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: December 12, 2017
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Ela Mia Cadag, Jefferson Talledo
  • Patent number: 9842828
    Abstract: One or more embodiments are directed to stacked packages, such as Package-on-Package (PoP) packages, that are stacked on a flexible folded substrate. The stacked packages have compliant corners. In particular, the stacked packages include an adhesive material at the corners between layers of the folded substrate. The adhesive material has a low modulus of elasticity, such as, for example, a modulus of elasticity of silicone adhesive. The low modulus of elasticity of the adhesive material produces compliant corners of the stacked package. The adhesive material fills openings between the folded substrate that are formed around a bottom semiconductor package of the stack package. In that regard, the bottom semiconductor package may have pulled back or recessed corners and the adhesive material fills the openings formed by the recessed corners. The recessed corners may be any size or shape.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: December 12, 2017
    Assignee: STMICROELECTRONICS, INC.
    Inventor: Jefferson Talledo
  • Patent number: 9818675
    Abstract: An integrated circuit (IC) device may include a leadframe and an IC die having a first surface coupled to the lead frame and a second surface opposite the first surface. The IC device may further include a conductive clip including a first portion coupled to the second surface of the IC die, a second portion coupled to the first portion and extending laterally away from the IC die, and at least one flexible lead coupled to the second portion and looping back under the second portion toward the leadframe. Furthermore, a package may be over the leadframe, IC die, and conductive clip and have an opening therein exposing the at least one flexible lead.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: November 14, 2017
    Assignee: STMicroelectronics, Inc.
    Inventors: Jefferson Talledo, Ela Mia Cadag