Patents by Inventor Jefferson Talledo

Jefferson Talledo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9768126
    Abstract: One or more embodiments are directed to semiconductor packages, including stacked packages, with one or more cantilever pads. In one embodiment a recess is located in a substrate of the package facing the cantilever pad. The cantilever pad includes a conductive pad on which a conductive ball is formed. The cantilever pad is configured to absorb stresses acting on the package.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: September 19, 2017
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Jefferson Talledo, Godfrey Dimayuga
  • Publication number: 20170162479
    Abstract: A semiconductor device may include a circuit board having an opening, and a frame. The frame may have an IC die pad in the opening, and arms extending outwardly from the IC die pad and coupled to the circuit board. The semiconductor device may include an IC mounted on the IC die pad, bond wires coupling the circuit board with the IC, and encapsulation material surrounding the IC, the bond wires, and the arms.
    Type: Application
    Filed: December 3, 2015
    Publication date: June 8, 2017
    Inventors: Jefferson TALLEDO, Rammil SEGUIDO
  • Publication number: 20170141014
    Abstract: One or more embodiments are directed to semiconductor packages having an integrated heatsink and methods of forming same. In one embodiment, a package includes a plurality of leads that support and enclose periphery portions of the semiconductor die. The leads have first and second, opposing surfaces that form outer surfaces of the package. The first surface of the leads may form a heatsink and the second surface of the leads form lands of the package for coupling to another device, substrate, or board. The package includes encapsulation material that surrounds the semiconductor die and located between upper portions of the leads. The package further includes a back filling material (or insulating material) that is below the semiconductor die and between lower portions of the leads.
    Type: Application
    Filed: November 18, 2015
    Publication date: May 18, 2017
    Inventors: Ela Mia CADAG, Jefferson TALLEDO
  • Publication number: 20170110340
    Abstract: Embodiments of the present disclosure are directed to a leadframe package with recesses formed in outer surface of the leads. The recesses are filled with a filler material, such as solder. The filler material in the recesses provides a wetable surface for filler material, such as solder, to adhere to during mounting of the package to another device, such as a printed circuit board (PCB). This enables strong solder joints between the leads of the package and the PCB. It also enables improved visual inspection of the solder joints after the package has been mounted.
    Type: Application
    Filed: December 28, 2016
    Publication date: April 20, 2017
    Inventors: Jefferson Talledo, Frederick Ray Gomez
  • Patent number: 9627224
    Abstract: A semiconductor device may include a multi-layer interconnect board having in stacked relation a lower conductive layer, a dielectric layer, and an upper conductive layer. The dielectric layer may have a recess formed with a bottom and sloping sidewall extending upwardly from the bottom. The upper conductive layer may include upper conductive traces extending across the sloping sidewall, and the lower conductive layer may include lower conductive traces. The semiconductor device may include vias extending between the lower and upper conductive layers, an IC carried by the multi-layer interconnect board in the recess, bond wires coupling upper conductive traces to the IC, and encapsulation material adjacent the IC and adjacent portions of the multi-layer interconnect board.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: April 18, 2017
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Godfrey Dimayuga, Jefferson Talledo
  • Patent number: 9578744
    Abstract: Embodiments of the present disclosure are directed to a leadframe package with recesses formed in outer surface of the leads. The recesses are filled with a filler material, such as solder. The filler material in the recesses provides a wetable surface for filler material, such as solder, to adhere to during mounting of the package to another device, such as a printed circuit board (PCB). This enables strong solder joints between the leads of the package and the PCB. It also enables improved visual inspection of the solder joints after the package has been mounted.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: February 21, 2017
    Assignee: STMicroelectronics, Inc.
    Inventors: Jefferson Talledo, Frederick Ray Gomez
  • Publication number: 20170005028
    Abstract: Embodiments of the present disclosure are directed to leadframes having the cantilevered extension that includes an integral support on the end of the lead nearest the die pad. A support integral to the leadframe allows the support to be built to the proper height to support the cantilevered lead in each package and reduces or eliminates the upward, downward, and side to side deflections caused or allowed by supports built-in to the tooling of the manufacturing equipment. Also, by building the support into the leadframe, the leadframes may be pretaped prior to the die attach and wire bonding steps of the manufacturing process.
    Type: Application
    Filed: June 30, 2015
    Publication date: January 5, 2017
    Inventor: Jefferson Talledo
  • Patent number: 9536756
    Abstract: One or more embodiments are directed to semiconductor packages that are assembled using a sacrificial material, that when removed, separates the assembled packages into individual packages. The sacrificial material may be removed by a blanket technique such that a mask, pattern, or alignment step is not needed. In one embodiment the sacrificial material is formed on the lead frame on a connecting bar of a lead frame between adjacent leads. After the molding step, the connecting bar is etched away exposing a surface of the sacrificial material. The sacrificial material is removed, thereby separating the assembled packages into individual packages.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: January 3, 2017
    Assignee: STMicroelectronics, Inc.
    Inventors: Jefferson Talledo, Amor Zapanta
  • Publication number: 20160379846
    Abstract: One or more embodiments are directed to semiconductor packages that are assembled using a sacrificial material, that when removed, separates the assembled packages into individual packages. The sacrificial material may be removed by a blanket technique such that a mask, pattern, or alignment step is not needed. In one embodiment the sacrificial material is formed on the lead frame on a connecting bar of a lead frame between adjacent leads. After the molding step, the connecting bar is etched away exposing a surface of the sacrificial material. The sacrificial material is removed, thereby separating the assembled packages into individual packages.
    Type: Application
    Filed: June 29, 2015
    Publication date: December 29, 2016
    Inventors: Jefferson Talledo, Amor Zapanta
  • Publication number: 20160379916
    Abstract: A method is for making a semiconductor device. The method may include providing a lead frame having a recess, forming a sacrificial material in the recess of the lead frame, and mounting an IC on the lead frame. The method may include encapsulating the IC and the lead frame, removing portions of the lead frame to define lead frame contacts for the IC, and removing the sacrificial material to define for each lead frame contact a solder anchoring tab extending outwardly at a lower region and defining a sidewall recess between opposing portions of the solder anchoring tab and the encapsulation material.
    Type: Application
    Filed: June 29, 2015
    Publication date: December 29, 2016
    Inventor: Jefferson TALLEDO
  • Patent number: 9490146
    Abstract: A semiconductor device may include an IC, and lead frame contact areas adjacent the IC. Each lead frame contact area may have a lead opening. The semiconductor device may include bond wires, each bond wire coupling a respective lead frame contact area with the IC. The semiconductor device may include encapsulation material surrounding the IC, the lead frame contact areas, and the bond wires, and leads. Each lead may extend through a respective lead opening and outwardly from the encapsulation material.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: November 8, 2016
    Assignee: STMICROELECTRONICS, INC.
    Inventor: Jefferson Talledo
  • Publication number: 20160293523
    Abstract: An integrated circuit (IC) device may include a leadframe and an IC die having a first surface coupled to the lead frame and a second surface opposite the first surface. The IC device may further include a conductive clip including a first portion coupled to the second surface of the IC die, a second portion coupled to the first portion and extending laterally away from the IC die, and at least one flexible lead coupled to the second portion and looping back under the second portion toward the leadframe. Furthermore, a package may be over the leadframe, IC die, and conductive clip and have an opening therein exposing the at least one flexible lead.
    Type: Application
    Filed: March 31, 2015
    Publication date: October 6, 2016
    Inventors: Jefferson Talledo, Ela Mia Cadag
  • Publication number: 20160293450
    Abstract: A semiconductor device may include a multi-layer interconnect board having in stacked relation a lower conductive layer, a dielectric layer, and an upper conductive layer. The dielectric layer may have a recess formed with a bottom and sloping sidewall extending upwardly from the bottom. The upper conductive layer may include upper conductive traces extending across the sloping sidewall, and the lower conductive layer may include lower conductive traces. The semiconductor device may include vias extending between the lower and upper conductive layers, an IC carried by the multi-layer interconnect board in the recess, bond wires coupling upper conductive traces to the IC, and encapsulation material adjacent the IC and adjacent portions of the multi-layer interconnect board.
    Type: Application
    Filed: March 30, 2015
    Publication date: October 6, 2016
    Inventors: Godfrey DIMAYUGA, Jefferson Talledo
  • Publication number: 20160190072
    Abstract: One or more embodiments are directed to semiconductor packages, including stacked packages, with one or more cantilever pads. In one embodiment a recess is located in a substrate of the package facing the cantilever pad. The cantilever pad includes a conductive pad on which a conductive ball is formed. The cantilever pad is configured to absorb stresses acting on the package.
    Type: Application
    Filed: May 26, 2015
    Publication date: June 30, 2016
    Inventors: Jefferson Talledo, Godfrey Dimayuga
  • Publication number: 20160190031
    Abstract: One or more embodiments are directed to semiconductor packages with one or more cantilever pads. In one embodiment a recess is located in a substrate of the package facing the cantilever pad. The cantilever pad includes a conductive pad on which a conductive ball is formed. The cantilever pad is configured to absorb stresses acting on the package.
    Type: Application
    Filed: December 24, 2014
    Publication date: June 30, 2016
    Inventors: Jefferson Talledo, Godfrey Dimayuga
  • Publication number: 20160183369
    Abstract: Embodiments of the present disclosure are directed to a leadframe package with recesses formed in outer surface of the leads. The recesses are filled with a filler material, such as solder. The filler material in the recesses provides a wetable surface for filler material, such as solder, to adhere to during mounting of the package to another device, such as a printed circuit board (PCB). This enables strong solder joints between the leads of the package and the PCB. It also enables improved visual inspection of the solder joints after the package has been mounted.
    Type: Application
    Filed: December 22, 2014
    Publication date: June 23, 2016
    Inventors: Jefferson Talledo, Frederick Ray Gomez
  • Publication number: 20160146692
    Abstract: A surface mounting device has one body of semiconductor material such as an ASIC, and a package surrounding the body. The package has a base region carrying the body, a cap and contact terminals. The base region has a Young's modulus lower than 5 MPa. For forming the device, the body is attached to a supporting frame including contact terminals and a die pad, separated by cavities; bonding wires are soldered to the body and to the contact terminals; an elastic material is molded so as to surround at least in part lateral sides of the body, fill the cavities of the supporting frame and cover the ends of the bonding wires on the contact terminals; and a cap is fixed to the base region. The die pad is then etched away.
    Type: Application
    Filed: September 22, 2015
    Publication date: May 26, 2016
    Inventors: Fulvio Vittorio Fontana, Jefferson Talledo
  • Publication number: 20150348879
    Abstract: A semiconductor device may include an IC, and lead frame contact areas adjacent the IC. Each lead frame contact area may have a lead opening. The semiconductor device may include bond wires, each bond wire coupling a respective lead frame contact area with the IC. The semiconductor device may include encapsulation material surrounding the IC, the lead frame contact areas, and the bond wires, and leads. Each lead may extend through a respective lead opening and outwardly from the encapsulation material.
    Type: Application
    Filed: June 2, 2014
    Publication date: December 3, 2015
    Applicant: STMICROELECTRONICS, INC.
    Inventor: Jefferson TALLEDO
  • Publication number: 20150348891
    Abstract: A method for making a semiconductor device may include bonding a top lead frame component, having recesses, with a bottom lead frame component to form a lead frame, the top and bottom lead frame components each including metal. The method may include mounting an IC on the lead frame, encapsulating the IC and the lead frame, and removing portions of the bottom lead frame component to define contacts for the IC.
    Type: Application
    Filed: June 2, 2014
    Publication date: December 3, 2015
    Applicant: STMICROELECTRONICS, INC.
    Inventor: Jefferson TALLEDO
  • Patent number: 9165867
    Abstract: A semiconductor device may include an integrated circuit (IC), and lead frame contact areas adjacent the IC. Each lead frame contact area may have an opening therein. The semiconductor device may include bond wires, each bond wire coupling a respective lead frame contact area with the IC. The semiconductor device may also include encapsulation material surrounding the IC, the lead frame contact areas, and the bond wires. Solder balls are within the respective opening.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: October 20, 2015
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Ela Mia Cadag, Jefferson Talledo