Patents by Inventor Jeffery A. NEULS

Jeffery A. NEULS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • INTEGRATED TRANSISTOR AND RESISTOR-DIODE-CAPACITOR SNUBBER
    Publication number: 20220407411
    Abstract: In some aspects, the techniques described herein relate to a circuit including: a metal-oxide semiconductor field-effect transistor (MOSFET) including a gate, a source, and a drain; and a snubber circuit coupled between the drain and the source, the snubber circuit including: a diode having a cathode and an anode, the cathode being coupled with the drain; a capacitor having a first terminal coupled with the anode, and a second terminal coupled with the source; and a resistor having a first terminal coupled with the anode and the first terminal of the capacitor, and a second terminal coupled with the source.
    Type: Application
    Filed: June 13, 2022
    Publication date: December 22, 2022
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Dean E. PROBST, Joseph Andrew YEDINAK, Balaji PADMANABHAN, Peter A. BURKE, Jeffery A. NEULS, Ashok CHALLA
  • Stacked transistor assembly with dual middle mounting clips
    Patent number: 11075148
    Abstract: A stacked assembly of semiconductor devices includes a mounting pad covering a first portion of a low-side semiconductor device, and a contact layer covering a second portion of the low-side semiconductor device. A first mounting clip electrically connected to the contact layer has a supporting portion joining the first mounting clip to a first lead frame portion. A second mounting clip attached to the mounting pad has a supporting portion joining the second mounting clip to a second lead frame portion. A high-side semiconductor device has a first terminal electrically connected to the first mounting clip and thereby to the contact layer, and a second terminal electrically connected to the second mounting clip.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: July 27, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jeffrey Peter Gambino, David T. Price, Jeffery A. Neuls, Dean E. Probst, Santosh Menon, Peter A. Burke, Bigildis Dosdos
  • Method of forming a semiconductor device
    Patent number: 11049956
    Abstract: In one embodiment, a method of forming a semiconductor device forms gate trenches in a semiconductor substrate. A portion of the material between the trenches is narrowed and another material is formed on sidewalls of the narrowed portion that is substantially not etched by an etchant that etches the material of the portion of the material between the trenches. Source and gate contact openings are formed together.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: June 29, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Dean E. Probst, Jeffery A. Neuls, Masaichi Eda, Peter A. Burke, Peter McGrath, Prasad Venkatraman
  • STACKED TRANSISTOR ASSEMBLY WITH DUAL MIDDLE MOUNTING CLIPS
    Publication number: 20210111106
    Abstract: A stacked assembly of semiconductor devices includes a mounting pad covering a first portion of a low-side semiconductor device, and a contact layer covering a second portion of the low-side semiconductor device. A first mounting clip electrically connected to the contact layer has a supporting portion joining the first mounting clip to a first lead frame portion. A second mounting clip attached to the mounting pad has a supporting portion joining the second mounting clip to a second lead frame portion. A high-side semiconductor device has a first terminal electrically connected to the first mounting clip and thereby to the contact layer, and a second terminal electrically connected to the second mounting clip.
    Type: Application
    Filed: November 6, 2019
    Publication date: April 15, 2021
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jeffrey Peter GAMBINO, David T. Price, Jeffery A. NEULS, Dean E. PROBST, Santosh MENON, Peter A. BURKE, Bigildis DOSDOS
  • METHOD OF FORMING A SEMICONDUCTOR DEVICE
    Publication number: 20200395468
    Abstract: In one embodiment, a method of forming a semiconductor device forms gate trenches in a semiconductor substrate. A portion of the material between the trenches is narrowed and another material is formed on sidewalls of the narrowed portion that is substantially not etched by an etchant that etches the material of the portion of the material between the trenches. Source and gate contact openings are formed together.
    Type: Application
    Filed: August 20, 2019
    Publication date: December 17, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Dean E. PROBST, Jeffery A. NEULS, Masaichi EDA, Peter A. BURKE, Peter McGRATH, Prasad VENKATRAMAN