Abstract: A method and apparatus for locating defects in an on-chip memory of an integrated circuit is presented. During a memory test of on-chip memory, a known data value is written to a word in the on-chip memory, and an output data value is read back from the same addressed word in memory. A comparison of the output data value and expected data value is performed within the integrated circuit, producing a comparison result indicating which of the bit cells in the addressed word have failed. The address and comparison result are transferred external to said integrated circuit and correspond to a bitmap entry in a bitmap. The execution of a full memory test results in a complete bitmap indicating all the failed cells of the on-chip memory.

Abstract: A highly flexible and complex BIST engine provides at-speed access, testing, characterization, and monitoring of on-chip memory arrays, independent of other chip circuitry such as a CPU core. Each BIST engine has a main control block, at least one address generation block having an address local control block and one or more address-data generation blocks, and at least one data generation block having a data local control block and one or more data generation blocks. Each of the local address and data control blocks are programmed independently to define operations that will be performed by the individual address and data generation blocks, respectively. The main control block in turn controls operation of the local address and data control blocks to effect desired testing, accessing, and monitoring of the on-chip memory arrays.

Abstract: An improved method and structure for generating addresses of a memory array facilitates the testing of a memory cell by generating the address of any adjacent memory cell to the memory cell under test. The address generation provides for movement to any adjacent memory cell, in any direction, including north, south, east, west, northeast, northwest, southeast, and southwest. The address of any memory cell, even the address of a non-adjacent memory cell, may be selectively generated by defining a current memory address, choosing one or more modes by which increment-generated, decrement-generated, or combination increment/decrement addresses that define a next memory address are generated, and generating the row address and the column address of the next memory address in accordance with interdependent row carry-out and column carry-out operations.

Abstract: A system and method are disclosed which provide the capability of repairing an optimum number of defective memory segments, such as RAM segments, in order to minimize the amount of unused repairing circuitry, such as fuses used for repairing defects within the memory. A preferred embodiment of the present invention provides a RAM block implemented such that the number of fuses required for repairing defects therein is proportional to the optimum number of defective segments capable of being repaired. A preferred embodiment allows for repairing an optimum number of defective segments, while being capable of repairing any of the segments (up to the optimum number) by mapping repair data to an appropriate defective segment.

Abstract: An improved method and structure for generating addresses of a memory array facilitates the testing of a memory cell by generating the address of any adjacent memory cell to the memory cell under test. The address generation provides for movement to any adjacent memory cell, in any direction, including north, south, east, west, northeast, northwest, southeast, and southwest. The address of any memory cell, even the address of a non-adjacent memory cell, may be selectively generated by exercising a programmable initialization feature.

Abstract: Disclosed herein is a method of measuring the offset voltages of a plurality of SRAM sense amplifiers. The method comprises applying a series of stepped differential voltages to the plurality of sense amplifiers. After applying each differential voltage, an SRAM read operation is performed. The output of each sense amplifier may be interpreted with respect to the applied differential voltages. The point where a sense amplifier's output changes polarity will indicate a sense amplifier's offset voltage characteristic. Apparatus disclosed for implementing the method provides apparatus for isolating offset voltage test circuitry from other components of the SRAM while the SRAM is in a normal operating mode.

Abstract: Disclosed herein is a method of measuring the offset voltages of a plurality of SRAM sense amplifiers. The method comprises applying a series of stepped differential voltages to the plurality of sense amplifiers. After applying each differential voltage, an SRAM read operation is performed. The output of each sense amplifier may be interpreted with respect to the applied differential voltages. The point where a sense amplifier's output changes polarity will indicate a sense amplifier's offset voltage characteristic. Apparatus disclosed for implementing the method provides apparatus for isolating offset voltage test circuitry from other components of the SRAM while the SRAM is in a normal operating mode.