Patents by Inventor Jeffery Carlos Bell

Jeffery Carlos Bell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Host clock effective delay range extension
    Patent number: 11573702
    Abstract: Devices and techniques are disclosed herein to extend a range of an effective delay of a delay circuit having a configurable delay limited to a first range of delay values with respect to a first edge of a clock signal. A selection circuit can selectively apply the configurable delay to a subsequent, second edge of the clock signal to extend the range of the effective delay of the delay circuit beyond the first range of delay values.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: February 7, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Claudio Giaccio, Erminio Di Martino, Jeffery Carlos Bell
  • HOST CLOCK EFFECTIVE DELAY RANGE EXTENSION
    Publication number: 20210286516
    Abstract: Devices and techniques are disclosed herein to extend a range of an effective delay of a delay circuit having a configurable delay limited to a first range of delay values with respect to a first edge of a clock signal. A selection circuit can selectively apply the configurable delay to a subsequent, second edge of the clock signal to extend the range of the effective delay of the delay circuit beyond the first range of delay values.
    Type: Application
    Filed: May 26, 2021
    Publication date: September 16, 2021
    Inventors: Claudio Giaccio, Erminio Di Martino, Jeffery Carlos Bell
  • Host clock effective delay range extension
    Patent number: 11042301
    Abstract: Devices and techniques are disclosed herein for applying an effective sampling delay at a host device to one of an input signal, such as from an embedded MultiMediaCard (eMMC) device, or a clock signal. The host device can apply a configurable delay to one of the input signal or the clock signal with respect to a first edge of the clock signal, sample the input signal using the clock signal according to the configurable delay, and selectively align the sampled input signal to a subsequent, second edge of the clock signal to extend the configurable delay of the host device.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: June 22, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Claudio Giaccio, Erminio Di Martino, Jeffery Carlos Bell
  • HOST CLOCK BIT SLIP CALIBRATION
    Publication number: 20200192570
    Abstract: Devices and techniques are disclosed herein for applying an effective sampling delay at a host device to one of an input signal, such as from an embedded MultiMediaCard (eMMC) device, or a clock signal. The host device can apply a configurable delay to one of the input signal or the clock signal with respect to a first edge of the clock signal, sample the input signal using the clock signal according to the configurable delay, and selectively align the sampled input signal to a subsequent, second edge of the clock signal to extend the configurable delay of the host device.
    Type: Application
    Filed: December 13, 2018
    Publication date: June 18, 2020
    Inventors: Claudio Giaccio, Erminio Di Martino, Jeffery Carlos Bell