Abstract: An integrated wafer probe card with a light source facing a device under test (DUT) side and enabling methodology are provided.

Abstract: A Method of determining a suitable integrated circuit (IC) timing specifications margin by considering the dynamic nature of pin-to-pin interactions in an automated manner is disclosed. Embodiments include initializing one or more sets of timing specification on one or more pins of an IC, wherein each set of timing specification has a plurality of variables; determining one or more error count (EC) for the IC within the one or more sets of timing specification based, at least in part, on total number of failed cycles; ranking the one or more sets of timing specification based, at least in part, on the one or more EC; and replacing at least one lowly ranked set of timing specification with at least one new set of timing specification.

Abstract: A method of forming a wedge-shaped fiber array and a bottom base according to a probing pad layout of a Si-Photonic device to enable optical, DC and RF mixed signal tests to be performed at the same time and the resulting device are provided. Embodiments include a bottom base; and a fiber array with sidewalls and a top surface having a first angle and a second angle, respectively, over the bottom base, wherein the fiber array is structured to expose bond pads of a Si-Photonic device during wafer level Si-Photonic testing.