Abstract: A memory controller utilizing a performance monitor to modulate the level of data security applied to the data being transferred to and from memory depending on the performance. The performance monitor tracks the response time for access to the memory over a defined time window. The response times are then compared to a predefined allowable response time. This comparison is done over a predefined window of time. When the actual response times exceed the allowable limits, the level of encryption is limited until performance parameters fall within the limits selected. The frequency with which the encryption mechanism is adjusted may also be predefined. Data transfers continue as the controller monitors system performance and controls the level of security applied to the data according to that performance data. The performance modulation can be different depending on what unit is accessing memory in multi-unit systems.

Abstract: A method and apparatus are provided for implementing seamless error resumption in a shared memory bus structure. Controls and data are stored for each read operation and each write operation. Each read operation and each write operation is monitored to determine when an error has occurred for either a read operation or a write operation. When an error has occurred for the read operation or the write operation, the error is suppressed and the stored controls and data are gated to continue the read operation or the write operation.

Abstract: An MPEG-2 compliant digital video encoder system having a refinement processor for reconstructive processing for I-picture and P-picture encoding. The refinement processor includes a frame difference unit which has a predicted error array (PE array). The predicted error array comprises a shared-use array for storing both luminance data and chrominance data of a macroblock of data. The predicted error array also comprises a dual-port structure and array read control logic which allows simultaneous reading and writing of data to the array. Address selector logic controls addressing of the PE array such that writing of luminance data and chrominance data to the PE array and reading of luminance data and chrominance data from the array remains synchronous.

Abstract: An MPEG digital video decoder system, method and computer program product are presented for monitoring decoding of an encoded digital video signal for one or more predefined illegal conditions. Error detection logic is coupled to the variable length (VLC) decoder, inverse quantizer (IQ), inverse discrete cosine transformer (IDCT) and motion compensator (MC) of the decoder for detecting an illegal condition within at least one of the VLC decoder, IQ, IDCT and MC during decoding of the encoded digital video signal. The monitored illegal conditions can include a VLC/IQ control error, an IQ level overrun, and IQ/IDCT buffer error, an MC idle error and an MC macroblock start error. Error signals are reported to a central error register which is monitored periodically by the decoder's control processor. The control processor initiates recovery within the decoder system prior to stoppage of the system due to the illegal condition.

Abstract: A scalable architecture MPEG2 compliant digital video encoder system having an I-frame video encoder module with a Discrete Cosine Transform processor, a quantization unit, a variable length encoder, a FIFO buffer, and a compressed store interface, for generating an I-frame containing bitstream. The system also includes a second processor element with a reference memory interface, motion estimation and compensation capability, inverse quantization, and inverse discrete cosine transformation, and motion compensation means; and at least one third processor element for motion estimation. According to the invention, the difference data between the current macroblock and the reference macroblock is stored, which may be of different formats, is storted in memory in a common format by blocking bits in an address counter of the memory.