Abstract: A scannable register array structure includes a plurality of individual latches, each configured to hold one bit of array data in a normal mode of operation. The plurality of individual latches operate in scannable latch pairs in a test mode of operation, with first latches of the scannable latch pairs comprising L1 latches and second latches of the scannable latch pairs comprising L2 latches. A test clock signal generates a first clock pulse signal, A, for the L1 latches and a second clock pulse signal, B, for the L2 latches. The L2 latches are further configured to selectively receive L1 data therein upon a separate activation of the B clock signal, independent of the test clock signal, such that a scan out operation of the individual latches results in observation of L1 latch data.

Abstract: A scannable register array structure includes a plurality of individual latches, each configured to hold one bit of array data in a normal mode of operation. The plurality of individual latches operate in scannable latch pairs in a test mode of operation, with first latches of the scannable latch pairs comprising L1 latches and second latches of the scannable latch pairs comprising L2 latches. A test clock signal generates a first clock pulse signal, A, for the L1 latches and a second clock pulse signal, B, for the L2 latches. The L2 latches are further configured to selectively receive L1 data therein upon a separate activation of the B clock signal, independent of the test clock signal, such that a scan out operation of the individual latches results in observation of L1 latch data.

Abstract: The embodiments of the invention provide an apparatus, method, etc. for an efficient circuit and method to measure resistance. A sense line driver for an integrated circuit memory is provided, including a sense node that receives an experiment signal from an experiment structure. An output device is connected to the sense node, wherein the output device amplifies the experiment signal. Further, a voltage divider is connected to the sense node, wherein the voltage divider includes a first device and a second device. A sensing range is controlled by an operating width/resistance range and/or an adjust signal of the second device. The adjust signal changes a gate to source voltage of the second device and holds a constant voltage over multiple sensing instances. The sensing range is different for each of the sensing instances due to a change in the operating width of the second device.

Abstract: Embodiments of the invention provide a method, computer program product, etc. for analysis techniques to reduce simulations to characterize the effect of variations in transistor circuits. A method of simulating transistors in an integrated circuit begins by reducing a group of parallel transistors to a single equivalent transistor. The equivalent transistor is subsequently simulated, wherein only a portion of the parallel transistors are simulated. Next, the integrated circuit is divided into channel-connected components and simulated for the channel-connected components. A table is created for each type of channel-connected component; and parameterized across chip variation equations are calculated from results of the integrated circuit simulation. Moreover, table entries are created, which include a number of transistor types, a number of unique transistor primitive patterns, and/or a number of paths through each of the transistor primitive patterns.

Abstract: The embodiments of the invention provide an apparatus, method, etc. for an efficient circuit and method to measure resistance. A sense line driver for an integrated circuit memory is provided, including a sense node that receives an experiment signal from an experiment structure. An output device is connected to the sense node, wherein the output device amplifies the experiment signal. Further, a voltage divider is connected to the sense node, wherein the voltage divider includes a first device and a second device. A sensing range is controlled by an operating width/resistance range and/or an adjust signal of the second device. The adjust signal changes a gate to source voltage of the second device and holds a constant voltage over multiple sensing instances. The sensing range is different for each of the sensing instances due to a change in the operating width of the second device.

Abstract: A method for providing memory cells that allow multiple variations of metal level assignments for bitlines and wordlines is disclosed. A memory cell includes two cell elements. The first and second cell elements are identically processed up to a metal-1 layer. The first cell element is subsequently processed with bitlines on a metal-2 layer and wordlines on a metal-3 layer. Next, the second cell element is processed with bitlines on the metal-3 layer and wordlines on the metal-2 layer.

Abstract: A detector circuit and method for detecting a silicon well voltage or current to indicate an alpha particle or cosmic ray strike of the silicon well. One significant application for the detection circuit of the present invention is for the redundancy repair latches that are used in SRAMs. The redundancy repair latches are normally written once at power-up to record failed latch data and are not normally written again. If one of the latches changes states due to an SER (Soft Error Rate-such as a strike by an alpha particle or cosmic ray) event, the repair data in the redundancy latches of the SRAM would now be incorrectly mapped. The detector circuit and method monitors the latches for the occurrence of an SER event, and responsive thereto issues a reload of the repair data to the redundancy repair latches.

Abstract: A zero threshold voltage (ZVt) pFET (104) and a method of making the same. The ZVt pFET is made by implanting a p-type substrate (112) with a retrograde n-well (116) so that a pocket (136) of the p-type substrate material remains adjacent the surface of the substrate. This is accomplished using an n-well mask (168) having a pocket-masking region (184) in the aperture (180) corresponding to the ZVt pFET. The n-well may be formed by first creating a ring-shaped precursor n-well (116?) and then annealing the substrate so as to cause the regions of the lower portion (140?) of the precursor n-well to merge with one another to isolate the pocket of p-type substrate material. After the n-well and isolated pocket of p-type substrate material have been formed, remaining structures of the ZVt pFET may be formed, such as a gate insulator (128), gate (132), source (120), and drain (124).

Abstract: A redundancy register architecture associated with a RAM provides for soft-error tolerance. An enable register provides soft error rate protection to the registers that contain replacement information for redundant rows and columns. The gate register determines whether a row or column replacement register contains a specific address, and parity protection to the replacement register is activated as necessitated. The register architecture is changed to make the register state a “don't care” state for the majority of the registers. A small number of registers that are critical to the redundancy system are identified and made more robust to upsets. Word-line and column-line substitution is implemented. A ripple parity scheme is implemented when parity checks are activated.

Abstract: A zero threshold voltage (ZVt) pFET (104) and a method of making the same. The ZVt pFET is made by implanting a p-type substrate (112) with a retrograde n-well (116) so that a pocket (136) of the p-type substrate material remains adjacent the surface of the substrate. This is accomplished using an n-well mask (168) having a pocket-masking region (184) in the aperture (180) corresponding to the ZVt pFET. The n-well may be formed by first creating a ring-shaped precursor n-well (116′) and then annealing the substrate so as to cause the regions of the lower portion (140′) of the precursor n-well to merge with one another to isolate the pocket of p-type substrate material. After the n-well and isolated pocket of p-type substrate material have been formed, remaining structures of the ZVt pFET may be formed, such as a gate insulator (128), gate (132), source (120), and drain (124).

Abstract: A zero threshold voltage (ZVt) pFET (104) and a method of making the same. The ZVt pFET is made by implanting a p-type substrate (112) with a retrograde n-well (116) so that a pocket (136) of the p-type substrate material remains adjacent the surface of the substrate. This is accomplished using an n-well mask (168) having a pocket-masking region (184) in the aperture (180) corresponding to the ZVt pFET. The n-well may be formed by first creating a ring-shaped precursor n-well (116′) and then annealing the substrate so as to cause the regions of the lower portion (140′) of the precursor n-well to merge with one another to isolate the pocket of p-type substrate material. After the n-well and isolated pocket of p-type substrate material have been formed, remaining structures of the ZVt pFET may be formed, such as a gate insulator (128), gate (132), source (120), and drain (124).

Abstract: A redundancy register architecture associated with a RAM provides for soft-error tolerance. An enable register provides soft error rate protection to the registers that contain replacement information for redundant rows and columns. The gate register determines whether a row or column replacement register contains a specific address, and parity protection to the replacement register is activated as necessitated. The register architecture is changed to make the register state a “don't care” state for the majority of the registers. A small number of registers that are critical to the redundancy system are identified and made more robust to upsets. Word-line and column-line substitution is implemented. A ripple parity scheme is implemented when parity checks are activated.

Abstract: A method and structure for a test structure that has an array of cells connected together by conductive lines. The conductive lines connect the cells together as if they were a single cell. The conductive lines can include common word line; a common bit line; a common bit line complement line, a common N-well voltage line, a common interior ground line, a common interior voltage line, and/or a common ground line.

Abstract: A compiler for building at least one compilable SRAM including at least one compilable sub-block. A global control clock generation circuit generates a global control signal. At least one local control logic and speed control circuit controls the at least one compilable sub-block. The local control logic and speed control circuit is controlled by the global control signal. An algorithm receives an input capacity and configuration for the sub-block of the SRAM array. An algorithm determines a number of wordlines and bitlines required to create the sub-block of the input capacity. An algorithm optimizes a cycle time of the sub-block by determining global control clock circuits based upon the number of wordlines and bitlines in the sub-block. An algorithm optimizes access time of the sub-block by determining local speed control circuits based upon the number of wordlines and bitlines.

Abstract: A precharge wordline decoder is disclosed that comprises a first logic circuit that receives a first clock signal from a clock driver for enabling the discharge element within the first logic circuit. The wordline decoder further comprises a delay circuit for generating a predetermined delayed clock signal from the first clock signal, the delayed clock signal being locally-controlled. A second logic circuit of the wordline decoder receives the delayed clock signal for controlling wordline driver elements. The first logic circuit also receives the delayed clock signal for disabling the precharge elements of the decoder.

Abstract: An improved configuration of a capacitor formed with FET technology and a resistor and/or conductor is provided. In this configuration a capacitor is formed in which the diffusion zone of the substrate is used as one plate of the capacitor and what would normally be the gate electrode of an FET is used as the other plate of the capacitor, with the two plates being separated by a conventional thin dielectric gate oxide layer. An insulator, such as silicon dioxide overlays the gate electrode, and electrical connections to the gate electrode and diffusion zone are made through the insulator to allow the two plates of the capacitor to be connected to various devices or components as required. The top surface of this insulation layer is also used to form metal resistors. Depending on the value of required resistance, a second insulating layer may be used and a second level of metal used to connect segments of the resistors formed on the first layer of metal to form a longer resistor.