Abstract: An improved content addressable memory includes a control circuit which, during a single clock pulse, receives and compares one search address on search address input terminals to compare addresses in N address registers, and simultaneously the control circuit conditionally writes a previously received search address into a selectable one of N address registers. With this improvement, the operating speed of the content addressable memory is increased since the writing of one search address into an address register and the searching with another search address does not require two separate clock cycles.

Abstract: An improved CAM (content addressable memory) cell is provided with dual address lines operable independently for a Read operation or for a Write operation. The cell is additionally provided with dual ports so that the first port permits a data input for Write operations or alternatively a data input for Search-Compare operations. The second port (Data Output) is independently connected to enable Read out of data residing in the cell. Each CAM cell also has a coincidence line (match-hit) output to indicate when an input Search bit or word coincides with resident data within the CAM cell. The CAM cells are arranged in an array of "m" rows with each row having "n" bits to hold a "n" bit word. Operationally the array permits both "Read" and "Search-Compare" operations to be accomplished in one clock cycle rather than the usual requirement of 3-4 clock cycles.