Abstract: The ease and versatility by which logic functions may be implemented in a semicustom CMOS gate array is substantially increased by disposing core cells within the gate array about a plane of mirror symmetry. Such a gate array is devised with mirror symmetry in two orthogonal directions. A memory design of general utility and with particular utility in a gate array is devised so as to operate with a programmable word length. The word length of the memory is programmed by choosing an appropriate integrated circuit metal mask option to be utilized in the memory circuit design at a data bus input and output mapping. In the event that the memory is entirely included within a large scale integrated circuit, such as a gate array, a circuit design is further devised for providing a self-test of the operability of such a fully included memory without the necessity of providing input/output pins communicating with the memory or other external test signals.