Abstract: A queue pointer manager contained in an integrated data controller is capable of controlling high speed data transfers between a high speed controlled data channel, a local processor bus and a dedicated local data bus. The overall design utilizes enhanced features of the Micro Channel architecture and data buffering to achieve maximum burst rates of 80 megabytes and to allow communications with 8, 16, 32 and 64 bit Micro Channel devices. Queued demands allow flexible programming of the Micro Channel master operations and reporting of completion statuses. The hardware control of command and status queuing functions increases the processing speed of control operations and reduces the need for software queuing. Extensive error checking/reporting, programming parameters, internal wrap self-test capability give the integrated data controller advanced functions as an input/output processor. The queue pointer manager also manages queue read and write pointers.

Abstract: An Asynchronous Communications Interface to Synchronous Circuit having three stages is disclosed. The first stage captures the control and data signals from an asynchronous bus and converts them into signals which are synchronous to the internal clocks of the interface chip. The second stage of the interface is a synchronous state machine which utilizes the synchronized signals generated by the first stage to determine the current state of the asynchronous bus. The third stage of the interface uses the data generated by the synchronous state machine and the control and data signal capture logic to validate the data in a synchronous manner. This allows further processing of the data from the asynchronous bus without the use of any further asynchronous logic or timing.

Abstract: A 1-bit token ring arbitration architecture where a plurality of chips which require access to a shared bus are coupled together in a ring is described. Each chip receives an arbitration in signal from the preceding member of the ring which is used to receive the token. Each chip transmits an arbitration out signal to the following member of the ring to send the token to the following member. In the preferred embodiment, the token appears as a 1 cycle active low pulse. An error signal notifies all the bus participants that a ring error has been detected. Preferably, the number of cycles the error signal is held active, the more severe the error. A request of bus (ROB) signal notifies the chip holding the token that another bus member needs to use the bus. The ROB signal allows the current holder of the token to maintain control of the bus if it has further processing on the bus as long as no other bus member needs the bus.

Abstract: A Micro Channel integrated circuit design capable of controlling high speed data and control transfers between a Micro Channel bus, a local processor, and a dedicated local data bus. The interface controller utilizes enhanced features of the Micro Channel and data buffering to achieve high speed data communications with various bit size Micro Channel devices. Queued commands are handled by flexibly programming the interface control operations. Interface control hardware increases the processing speed of data transfers by implementing performance critical functions of queuing in hardware. Extensive error checking and reporting and self-test give the interface controller advance functions as an input/output processor.