Abstract: A memory system with non-volatile integrated circuit memory devices including an interface for a high speed bus is described, supporting continuous writes at the bus speed, without the possibility of buffer overrun during most conditions. The system comprises an memory bus, an system buffer, an array of non-volatile storage units, such as flash memory devices, and an interconnect system supporting data transfer among the components. The array includes sets and subsets of non-volatile storage units, referred to herein for convenience as platters having multiple banks, banks having multiple columns, and columns having multiple storage units. The storage units comprises integrated circuit memory having page buffers, with input ports. In one example, the array includes two platters, eight banks per platter, four columns per bank, and eight storage units per column, for a total of 256 storage units. The system buffer includes at least the same number of stores as columns in each bank.

Abstract: A memory system with non-volatile integrated circuit memory devices including an interface for a high speed bus is described, supporting continuous writes at the bus speed, without the possibility of buffer overrun during most conditions. The system comprises an memory bus, an system buffer, an array of non-volatile storage units, such as flash memory devices, and an interconnect system supporting data transfer among the components. The array includes sets and subsets of non-volatile storage units, referred to herein for convenience as platters having multiple banks, banks having multiple columns, and columns having multiple storage units. The storage units comprises integrated circuit memory having page buffers, with input ports. In one example, the array includes two platters, eight banks per platter, four columns per bank, and eight storage units per column, for a total of 256 storage units. The system buffer includes at least the same number of stores as columns in each bank.

Abstract: A storage server comprising: a processing unit, a bus system coupled with the processing unit, including a plurality of slots, slots in the plurality of slots including interfaces to respective data stores; a communication interface; and an operating system coupled with the processing unit the operating system including: logic controlling transfers among the plurality of slots over the bus system according to an internal format, logic for translating a storage transaction received over the communication interface into the internal format, and logic for configuring the plurality of slots according to a configuration data.

Abstract: An apparatus is described, comprising a plurality of banks, each bank having a number of columns of non-volatile storage units, each non-volatile storage unit having an input buffer for storing a page of data, the page having an input coupled to the input buffer accepting an input portion of data of a page at a memory speed, the non-volatile storage units storing the data from the input buffer within a memory write time; a plurality of interface buffers; an input bus having an input bus speed which is faster than the memory speed, the input bus being coupled to the plurality of interface buffers; a bus system, connecting each of the plurality of interface buffers to the non-volatile storage units of a column in each of the plurality of banks, supplying data from the plurality of interface buffers to the inputs of the non-volatile storage units at the memory speed.

Abstract: An assembly that engages a component to a computer system includes a cover adapted to retain the component and to be inserted within a chassis of the computer system. A slide movably coupled to the cover has a proximal position associated with inserting the cover into the chassis and a distal position associated with withdrawing the cover from the chassis. A detector coupled to a lock and to the slide detects movement of the slide to actuate the lock. The lock is coupled to the slide and to the detector, and blocks movement of the slide towards the distal point when the lock is in an engaged state.