Patents by Inventor Jeffery Scott Hunt
Jeffery Scott Hunt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7808275Abstract: Disclosed is a circuit comprising an inverter circuit which comprises inverters and level shifters; and a modulation circuit comprising a pull-up circuit and a pull-down circuit, the modulation circuit coupled to the inverter circuit to regulate the response of the circuit to an input voltage for various power supply voltage levels by the pull-up or pull-down circuit. Other embodiments are also disclosed.Type: GrantFiled: June 4, 2007Date of Patent: October 5, 2010Assignee: Cypress Semiconductor CorporationInventors: George McCollough Ansel, Jeffery Scott Hunt, Anand Kumar Chamakura
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Patent number: 7479800Abstract: A variable impedance sense (VIS) circuit (600) can detect and store an input offset value inherent in a sensing loop (620 and/or 622). According to a detected input offset polarity, a resulting impedance matching binary code can be adjusted to compensate for error that can be introduced by the input offset. The binary code can also be adjusted to compensate for additional error that can be introduced by dropping a least significant bit (LSB) of the code to reduce noise effects caused by the switching of the LSB.Type: GrantFiled: September 28, 2006Date of Patent: January 20, 2009Assignee: Cypress Semiconductor CorporationInventors: Kalyana C. Vullaganti, Jeffery Scott Hunt
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Patent number: 7139292Abstract: An apparatus comprising a distributed multiplexer configured to receive a distributed input group of signals. The distributed multiplexer may be configured to evenly load the distributed input groups.Type: GrantFiled: August 31, 2001Date of Patent: November 21, 2006Assignee: Cypress Semiconductor Corp.Inventors: Brian P. Evans, Jeffery Scott Hunt
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Patent number: 7132854Abstract: A data path (200) can be configured to accommodate different clocking arrangements. In one mode, data values may be output at a single data rate: one data value every clock cycle. In another mode, data values may be output at a double data rate: two data values every clock cycle. A data path (200) can be compact circuit structure, needing only an additional mode multiplexer (206) and inverter over a conventional D-type master-slave flip-flop.Type: GrantFiled: September 23, 2004Date of Patent: November 7, 2006Assignee: Cypress Semiconductor CorporationInventors: Suwei Chen, Sanjay Sancheti, Jeffery Scott Hunt
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Patent number: 7113445Abstract: A multi-port memory cell (200) can be formed from seven transistors. Single ended write operations can be performed without a boosted word line voltage or variable power supply. A data value (D/DB) stored in the memory cell (200) can be cleared by shorting complementary data nodes (204-0 and 204-1) together. Write data can then be placed on a bit line. Complementary data nodes (204-0 and 204-1) can then be isolated once again, resulting in the write data being latched within the memory cell (300). An access method (700) for a multi-port memory cell is also described.Type: GrantFiled: September 22, 2004Date of Patent: September 26, 2006Assignee: Cypress Semiconductor CorporationInventors: Sanjay Sancheti, Jeffery Scott Hunt, George M. Ansel
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Patent number: 6904436Abstract: A method and system for automatically building a bit order data structure of configuration bits for a programmable logic device. One embodiment of the present invention first identifies a plurality of memory cells in a hierarchical schematic representation of the programmable device. Next, this embodiment determines a plurality of addresses corresponding to the plurality of memory cells. This embodiment next determines a plurality of logical names for the plurality of memory cells. Then, based on an order in which the plurality of addresses are to be loaded into the programmable logic device, this embodiment orders the plurality of logical names for the plurality of memory cells. Another embodiment first accesses a database comprising a plurality of logical names corresponding to a plurality of addresses. Then, this embodiment accesses a database specifying an order in which the plurality of addresses are to be loaded into the programmable logic device.Type: GrantFiled: October 4, 2000Date of Patent: June 7, 2005Assignee: Cypress Semiconductor CorporationInventors: James Daniel Merchant, Gordon Carskadon, Brian P. Evans, Jeffery Scott Hunt, Anup Nayak, Andrew Wright
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Patent number: 6815984Abstract: An apparatus comprising an input section and an output section. The input section may be configured to generate a first control signal and a second control signal in response to an input signal and a select signal. The output section may be configured to generate an output signal in response to the first and second control signals. The output signal may be (i) related to the input signal when in a first mode and (ii) disabled when in a second mode.Type: GrantFiled: August 27, 2001Date of Patent: November 9, 2004Assignee: Cypress Semiconductor Corp.Inventors: Benjamin J. Bowers, Brian P. Evans, Jeffery Scott Hunt
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Patent number: 6801064Abstract: A buffer includes a pull-up level shifter coupled to an input signal. A pull-down level shifter separate from the pull-up level shifter is coupled to the input signal. A driver is coupled to the pull-up level shifter and the pull-down level shifter.Type: GrantFiled: August 27, 2002Date of Patent: October 5, 2004Assignee: Cypress Semiconductor, CorpInventors: Jeffery Scott Hunt, Scott Anthony Jackson
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Patent number: 6784717Abstract: An input buffer system has an input clipping circuit. The input clipping circuit has a high voltage input and uses transistors all being the thin oxide type transistors. A high voltage detect circuit is coupled to the input clipping circuit. An input buffer circuit is coupled to the input clipping circuit and has a low voltage output range.Type: GrantFiled: August 28, 2002Date of Patent: August 31, 2004Assignee: Cypress Semiconductor CorporationInventors: Jeffery Scott Hunt, Scott Anthony Jackson
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Patent number: 6609243Abstract: An apparatus comprising a first stage and a second stage. The first stage may comprise a first section and a second section. The second stage may be embedded between the first and second sections. The first and second stages may be configured to equalize signal paths between a plurality of inputs of the first stage and a plurality of outputs of the second stage.Type: GrantFiled: August 29, 2001Date of Patent: August 19, 2003Assignee: Cypress Semiconductor Corp.Inventors: Brian P. Evans, Jeffery Scott Hunt
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Patent number: 6532524Abstract: An apparatus comprising a first compare circuit, a second compare circuit and a memory. The first compare circuit may be configured to present a first match signal in response to a first address and a second address. The second compare circuit may be configured to present a second match signal in response to the first match signal, a first write enable signal and a second write enable signal. The memory may also be configured to present the first and second write enable signals. In one example, the memory may be configured to store and retrieve data with zero waiting cycles in response to the second match signal.Type: GrantFiled: March 30, 2000Date of Patent: March 11, 2003Assignee: Cypress Semiconductor Corp.Inventors: Junfei Fan, Jeffery Scott Hunt
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Patent number: 6490712Abstract: A method and system for automatically identifying configuration cell addresses in a schematic hierarchy is disclosed. In one embodiment of the present invention, a memory cell (e.g., a configuration bit) is identified in a schematic hierarchy. Next, this embodiment determines an address for the memory cell. Then, this embodiment determines a unique name for the memory cell. The name is comprised of a hierarchical logical name and a schematic path name. By traversing the schematic and using logical names, all addresses of configuration bits of a circuit design may be automatically determined. The process is repeated for each memory cell in the schematic. This embodiment stores the unique name of the configuration bit and the address of the configuration bit in a data structure.Type: GrantFiled: October 4, 2000Date of Patent: December 3, 2002Assignee: Cypress Semiconductor CorporationInventors: James Daniel Merchant, Gordon Carskadon, Brian P. Evans, Jeffery Scott Hunt, Anup Nayak, Andrew Wright
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Patent number: 6483386Abstract: An apparatus comprising a native device coupled to an input of an amplifier. The native device is configured to provide a high voltage protection in response to an enable signal.Type: GrantFiled: September 29, 2000Date of Patent: November 19, 2002Assignee: Cypress Semiconductor Corp.Inventors: Daniel E. Cress, Jeffery Scott Hunt
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Patent number: 6473357Abstract: An apparatus comprising a memory array having a first port and a one or more other ports and a control circuit configured to couple (i) a bitline of the first port to a corresponding bitline of the one or more other ports and (ii) a dataline of the first port to a corresponding dataline of the one or more other ports in response to the first port and the one or more other ports accessing a common address.Type: GrantFiled: September 29, 2000Date of Patent: October 29, 2002Assignee: Cypress Semiconductor CorporationInventors: Junfei Fan, Jeffery Scott Hunt, Daniel E. Cress
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Patent number: 6388469Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a first control signal and a second control signal in response to (i) a first input signal, (ii) a second input signal and (iii) a voltage control signal. The second circuit configured to generate (i) an output signal in response to the first and the second control signals and (ii) the voltage control signal in response to a pad voltage.Type: GrantFiled: August 13, 1999Date of Patent: May 14, 2002Assignee: Cypress Semiconductor Corp.Inventors: Jeffery Scott Hunt, Muthukumar Nagarajan
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Patent number: 6353336Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a first output signal in response to one or more first input signals. The second circuit may be configured to generate a second output signal in response to one or more second input signals. The first and second output signals may be presented to a bond pad.Type: GrantFiled: March 24, 2000Date of Patent: March 5, 2002Assignee: Cypress Semiconductor Corp.Inventors: David R. Lindley, William G. Baker, Jeffery Scott Hunt
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Patent number: 6191636Abstract: A circuit is presented comprising a first device and a second device. The first device may be configured to operate at a first supply voltage and may be configured to generate a pull-up signal in response to an input signal. The second device may be configured to operate at a second supply voltage. The second supply voltage may be lower than the first supply voltage. The second device may be configured to generate an output in response to (i) the input signal and (ii) the pull-up signal.Type: GrantFiled: September 22, 1999Date of Patent: February 20, 2001Assignee: Cypress Semiconductor Corp.Inventors: Daniel Eric Cress, Jeffery Scott Hunt, Muthu Nagarajan
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Patent number: 6122203Abstract: A circuit and method comprising a memory, a first latch, a second latch and a control circuit. The memory may be configured to write information in response to (i) an input data signal and (ii) an address signal. The first latch may be configured to hold the address in response to a control signal. The second latch may be configured to hold the data input signal in response to the control signal. The control circuit may be configured to present the control signal in response to (i) an enable signal and (ii) a detect signal.Type: GrantFiled: June 29, 1998Date of Patent: September 19, 2000Assignee: Cypress Semiconductor Corp.Inventors: Jeffery Scott Hunt, Sudhaker Reddy Anumula, Ajay Srikrishna, Jeffrey W. Waldrip, Satish C. Saripella
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Patent number: 6087858Abstract: A circuit and method for generating an evaluation signal used to turn OFF one or more sense amplifiers. The sense amplifiers may be configured to present a first and second output in response to (i) an input signal and (ii) an enable signal. A detect circuit may be configured to present a detect signal in response to the first and second outputs. A control circuit may be configured to present the enable signal in response to (i) the detect signal and (ii) a wordline signal.Type: GrantFiled: June 24, 1998Date of Patent: July 11, 2000Assignee: Cypress Semiconductor Corp.Inventors: Jeffery Scott Hunt, Satish C. Saripella
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Patent number: 5986970Abstract: A circuit and method comprising a memory, a first latch, a second latch and a control circuit. The memory may be configured to write information in response to (i) an input data signal and (ii) an address signal. The first latch may be configured to hold the address in response to a control signal. The second latch may be configured to hold the data input signal in response to the control signal. The control circuit may be configured to present the control signal in response to (i) a detect signal and (ii) a transition of the address signal.Type: GrantFiled: June 29, 1998Date of Patent: November 16, 1999Assignee: Cypress Semiconductor Corp.Inventors: Jeffery Scott Hunt, Sudhaker Reddy Anumula, Ajay Srikrishna, Jeffrey W. Waldrip, Satish C. Saripella