Abstract: A scalable switch fabric using optical interconnects includes one or more line modules each including fabric interface optics supporting a plurality of optical output signals; an optical interconnect optically connected to each of the one or more line modules via the fabric interface optics; and one or more center stage switches, wherein the optical interconnect is adapted to shuffle the plurality of optical output signals from each of the one or more line modules to the one or more center stage switches. The optical interconnect can include two levels of shuffle to distribute each of the plurality of optical signals from each of the fabric interface optics to the one or more center stage switches.

Abstract: A scalable switch fabric using optical interconnects includes one or more line modules each including fabric interface optics supporting a plurality of optical output signals; an optical interconnect optically connected to each of the one or more line modules via the fabric interface optics; and one or more center stage switches, wherein the optical interconnect is adapted to shuffle the plurality of optical output signals from each of the one or more line modules to the one or more center stage switches. The optical interconnect can include two levels of shuffle to distribute each of the plurality of optical signals from each of the fabric interface optics to the one or more center stage switches.

Abstract: Circuit systems and methods use prime number interleave optimization for byte lane to time slice conversion of incoming data streams. Generally, the systems and methods buffer data for at least a number of samples equal to the number of byte lanes. Then the samples are transferred to a bank of buffers whose width is the smallest prime number greater than or equal to the number of byte lanes, N. Thus, the systems and methods utilize P minus N phantom lanes. As data is transferred, the data is circularly interleaved (position*N modulo P) so that all data which will be needed at the same time wind up in different readable devices, i.e. the buffers. By appropriate addressing, the data in the different readable devices may then be read in the form of time slices. The process can be reversed for time slice to byte lane conversion.

Abstract: Circuit systems and methods use prime number interleave optimization for byte lane to time slice conversion of incoming data streams. Generally, the systems and methods buffer data for at least a number of samples equal to the number of byte lanes. Then the samples are transferred to a bank of buffers whose width is the smallest prime number greater than or equal to the number of byte lanes, N. Thus, the systems and methods utilize P minus N phantom lanes. As data is transferred, the data is circularly interleaved (position * N modulo P) so that all data which will be needed at the same time wind up in different readable devices, i.e. the buffers. By appropriate addressing, the data in the different readable devices may then be read in the form of time slices. The process can be reversed for time slice to byte lane conversion.

Abstract: The present invention provides systems and methods for an efficient, parallel implementation of burst error correction codes, such as the Fire code. The present invention includes a FEC decoder which is pipelined to simultaneously perform syndrome computation, error trapping and syndrome normalization, and error correction. The pipelined implementation can apply to shortened and full-length codes. Advantageously, the present invention yields a design which is approximately 1/20th the size of conventional parallel approaches.

Abstract: The present invention provides systems and methods for an efficient, parallel implementation of burst error correction codes, such as the Fire code. The present invention includes a FEC decoder which is pipelined to simultaneously perform syndrome computation, error trapping and syndrome normalization, and error correction. The pipelined implementation can apply to shortened and full-length codes. Advantageously, the present invention yields a design which is approximately 1/20th the size of conventional parallel approaches.

Abstract: A method and apparatus for performing quickly and efficiently generating the error correction polynomial. In accordance with the present invention, multiple coefficients of the syndrome vector are processed in parallel by a Berlekamp algorithm logic block of the present invention. The Berlekamp algorithm's iterations can be performed in less than 60 clock cycles for a large order error correction polynomial, thereby enabling the polynomial to be generated very rapidly. In order to perform the Berlekamp algorithm at such a high rate of speed, Galois field multiplier logic is utilized in performing the algorithm.

Abstract: A method and apparatus for generating and inserting bit errors in data words that have been encoded in a forward error correction (FEC) system in order to estimate power dissipation. In accordance with the present invention, it has been determined that a burst error generator that is capable of erroring the maximum number of correctable data bits in every FEC encoded frame, which allows the designer to accurately produce test vectors that are suitable for use in commercially available power estimation tools. In addition, after the IC is produced, the burst error generator of the present invention can be enabled to provide real-time FEC power dissipation data for use in system thermal modeling, thus obviating the need to use costly external devices that emulate a given error rate.

Abstract: The present invention provides a method and apparatus for quickly and efficiently processing an error correction polynomial to locate bit errors using a Chien search algorithm. In accordance with the present invention, it has been determined that multiplying the ? coefficients of the error locator polynomial by a scaling vector prior to performing the Chien search algorithm matrix operations, it possible to use constant coefficients in the matrix multiply logic. This enables a relatively small amount of logic to be used to perform the matrix multiplication operations of the Chien search algorithm. The Chien search algorithm logic of the present invention is configured to perform many matrix multiply operations in parallel, which enables the Chien search algorithm to be executed very quickly to locate the bit errors in the error locator polynomial. Such a large number of matrix multiply operations would normally require a very large number of gates.

Abstract: A method and apparatus for performing syndrome computation in a decoder of a forward error correction (FEC) system. Syndrome computation logic of the decoder uses a partial parity-check matrix to recursively generate intermediate syndrome vectors based on a code word received by the decoder and to modulo-2 add the recursively generated intermediate syndrome vectors together until a final resolved syndrome vector has been generated. This recursive use of the partial parity-check matrix enables the syndrome computations to be performed very quickly so that the decoder is suitable for use in high data rate systems and provides a very large reduction in the amount of logic needed to perform the syndrome vector computations. The reduction in the syndrome computation logic results in reduced area requirements for the logic as well as reduced power requirements.

Abstract: A method and apparatus that enable a Poisson distribution to be approximated by generating random bit sequences over a number of clock cycles. The apparatus of the present invention comprises a Poisson distribution module that includes logic configured to modulo-2 add at least two pseudo-random bit sequences (PRBSs) together to generate a number of PRBSs, which are then compared to a threshold bit sequence. The result of the comparison is a random bit sequence. Over a number of clock cycles, the random bit sequences produced approximate a Poisson distribution. The present invention can be used to evaluate the performance of communications systems by modulo-2 adding these random bit sequences with encoded data words to insert errors into the encoded data words, and then determining how well the communications system decodes and corrects the errors in the encoded data words.

Abstract: A method and apparatus for performing parity bit generation. The apparatus of the present invention comprises a parity bit generator that multiplies words comprising message bits by a partial parity multiplication sub-matrix to generate intermediate parity values, and recursively adds (modulo-2) respective intermediate values together so that by the end of the recursive process, a final parity vector exists. This final parity vector can then be added to a message word to create a code word. By recursively using the partial parity multiplication sub-matrix in this way, the number of gates needed to perform parity bit generation is kept relatively small. Consequently the amount of power consumed by the parity bit generator during parity bit generation is relatively small. This is in contrast to typical parity bit generators, which multiply all of the message bits by a full parity multiplication matrix without recursion.