Abstract: Systems and methods include receiving (51) blocks of data that has been Forward Error Correction (FEC) encoded via Open Forward Error Correction (OFEC) adaptation; decoding (52) the blocks of data; processing (53) checksum data that is included in padding data required in the OFEC adaptation, wherein the padding data is distributed across N rows of payload data; and determining (54) a location of any errors in the payload data based on the processed checksum data. The OFEC adaptation is for mapping the blocks of data into any of a FlexO structure, a ZR structure, and variants thereof, and the location of any errors can be used for error marking.

Abstract: A coherent optical modem includes an optical interface; and circuitry connected to the optical interface and configured to detect a first timing reference point in a transmit Digital Signal Processor (DSP) frame in a transmit direction from a first node to a second node, and detect a second timing reference point in a receive DSP frame in a receive direction from the second node to the first node, wherein the first timing reference point and the second timing reference point are determined based on a pattern in any DSP frame field including i) padding area, ii) a reserved area, and iii) a DSP Multi-Frame Alignment Signal (MFAS) area. The pattern can be input in select DSP frames for a time period that is greater than a time period for each DSP frame.

Abstract: A coherent optical modem includes an optical interface; and circuitry connected to the optical interface and configured to detect a first timing reference point in a transmit Digital Signal Processor (DSP) frame in a transmit direction from a first node to a second node, and detect a second timing reference point in a receive DSP frame in a receive direction from the second node to the first node, wherein the first timing reference point and the second timing reference point are determined based on a pattern in any DSP frame field including i) padding area, ii) a reserved area, and iii) a DSP Multi-Frame Alignment Signal (MFAS) area. The pattern can be input in select DSP frames for a time period that is greater than a time period for each DSP frame.

Abstract: Systems and methods include receiving blocks of data that has been Forward Error Correction (FEC) encoded via Open Forward Error Correction (OFEC) adaptation; decoding the blocks of data; processing Cyclic Redundancy Check (CRC) data that is included in padding data required in the OFEC adaptation, wherein the padding data is distributed across N rows of payload data; and determining a location of any errors in the payload data based on the processed CRC data. The OFEC adaptation is for mapping the blocks of data into any of a FlexO-x frame structure, a ZR frame structure, and variants thereof, and the location of any errors can be used for error marking.

Abstract: A line module configured to provide a protected transponded service includes a plurality of ports; switch interface circuitry communicatively coupled to a switch module; and interface circuitry communicatively coupled to the plurality of ports and the switch interface circuitry, wherein the interface circuitry includes a cross-point switch between the plurality of ports and the switch interface circuitry; wherein bandwidth of the plurality of ports is greater than bandwidth of the switch interface circuitry to the switch module; and wherein the protected transponded service is configured between the plurality of ports directly via the interface circuitry and is selectively routed to the switch module via the switch interface circuitry for restoration thereof, responsive to a failure.

Abstract: The present disclosure provides a structured, pipelined large time-space switch and method of operation resolving interconnect complexity. The time-space switch results in an interconnect complexity that does not grow as the spatial dimension is increased and results in a reduction of long high fan-out nets, a quicker layout, and improved clock speed. With respect to time-space switch fabric implementation, the present invention improves the maximum clock frequency of the switch fabric, and improves integrated circuit layout time by eliminating long high fan-out nets. Certain high-speed large switch fabrics may not be realizable without this implementation, and it significantly reduces implementation time (and cost).

Abstract: An Optical channel Data Unit flex (ODUflex) resizing method, node, and network include determining that the ODUflex needs resizing, wherein the ODUflex is configured in the network on a current path between the node and a second node in the network; when the resizing is a decrease, reducing a size of the ODUflex by i) a resize decrease operation using a control plane or ii) a Link Aggregation Group and Make-Before-Break operation; and, when the resizing is an increase, increasing a size of the ODUflex by i) a resize increase operation using a control plane or ii) a Link Aggregation Group and Make-Before-Break operation. The method provides hitless resizing without using ITU Recommendation G.7044/Y.1347 (10/11) and can perform the reducing or the increasing changing bandwidth of the ODUflex by approximately 100 G in less than a second.

Abstract: An Optical channel Data Unit flex (ODUflex) resizing method, node, and network include determining that the ODUflex needs resizing, wherein the ODUflex is configured in the network on a current path between the node and a second node in the network; when the resizing is a decrease, reducing a size of the ODUflex by i) a resize decrease operation using a control plane or ii) a Link Aggregation Group and Make-Before-Break operation; and, when the resizing is an increase, increasing a size of the ODUflex by i) a resize increase operation using a control plane or ii) a Link Aggregation Group and Make-Before-Break operation. The method provides hitless resizing without using ITU Recommendation G.7044/Y.1347 (10/11) and can perform the reducing or the increasing changing bandwidth of the ODUflex by approximately 100 G in less than a second.

Abstract: A time-space switch in a ring architecture includes input circuitry including N links each receiving M timeslots, a two-dimensional matrix of a plurality of switching circuits, the two-dimensional matrix is configured to receive from the input circuitry each of the M timeslots from the N links in a pipelined manner, and output circuitry including N links configured to receive any of the M timeslots from any of the N links from the two-dimensional matrix. The input circuitry, the two-dimensional matrix, and the output circuitry are arranged in a ring architecture therebetween. A link encoding protocol method performed in electrical circuitry includes receiving a plurality of time slots, grouping the plurality of time slots into time slot groups, performing a cyclic redundancy check between adjacent time slot groups, 64/65B encoding the time slot groups, and forward error correction encoding a plurality of 65B codewords from the 64/65B encoding.

Abstract: The present disclosure provides systems and methods for inserting pseudo-noise in a data stream based on an unacceptable input data sequence in an optical network thereby preventing unnecessary loss of frame in SONET/SDH or Optical Transport Network (OTN) systems. The present disclosure includes a SONET/SDH or OTN framer, a transceiver, and a method for detecting an unacceptable data sequence or pattern and inserting a keep-alive or pseudo-noise sequence in the data sequence to maintaining framing on subsequent network elements, framers, transceivers, etc. For example, the present invention, upon receiving an unacceptable pattern of zeros or low ones density caused by a loss of signal condition or the like, may insert a pseudorandom noise pattern into the transmitted frame. This allows the downstream network element to continue a frame lock on the incoming signal, and thus keep the frame overhead and data communications channels from being lost.

Abstract: The present disclosure provides systems and methods for real-time, in-service latency measurements over optical links that may be further integrated within various optical control planes. The present invention may utilize minimal unused overhead to calculate latency of an optical line through a transport network. The present invention utilizes timers at two end-point nodes associated with the optical line, and includes a mechanism to filter out frame skew between the nodes. Advantageously, the present invention provides a highly accurate latency measurement that may calculate latency on links as small as one meter, an in-service algorithm operable without network impact, and may be integrated with an optical control plane to automatically provide administrative weight variables associated with link costs.

Abstract: The present disclosure provides a structured, pipelined large time-space switch and method of operation resolving interconnect complexity. The time-space switch results in an interconnect complexity that does not grow as the spatial dimension is increased and results in a reduction of long high fan-out nets, a quicker layout, and improved clock speed. With respect to time-space switch fabric implementation, the present invention improves the maximum clock frequency of the switch fabric, and improves integrated circuit layout time by eliminating long high fan-out nets. Certain high-speed large switch fabrics may not be realizable without this implementation, and it significantly reduces implementation time (and cost).

Abstract: The present disclosure provides systems and methods for inserting pseudo-noise in a data stream based on an unacceptable input data sequence in an optical network thereby preventing unnecessary loss of frame in SONET/SDH or Optical Transport Network (OTN) systems. The present disclosure includes a SONET/SDH or OTN framer, a transceiver, and a method for detecting an unacceptable data sequence or pattern and inserting a keep-alive or pseudo-noise sequence in the data sequence to maintaining framing on subsequent network elements, framers, transceivers, etc. For example, the present invention, upon receiving an unacceptable pattern of zeros or low ones density caused by a loss of signal condition or the like, may insert a pseudorandom noise pattern into the transmitted frame. This allows the downstream network element to continue a frame lock on the incoming signal, and thus keep the frame overhead and data communications channels from being lost.

Abstract: The present disclosure provides systems and methods for real-time, in-service latency measurements over optical links that may be further integrated within various optical control planes. The present invention may utilize minimal unused overhead to calculate latency of an optical line through a transport network. The present invention utilizes timers at two end-point nodes associated with the optical line, and includes a mechanism to filter out frame skew between the nodes. Advantageously, the present invention provides a highly accurate latency measurement that may calculate latency on links as small as one meter, an in-service algorithm operable without network impact, and may be integrated with an optical control plane to automatically provide administrative weight variables associated with link costs.