Patents by Inventor Jeffory L. Smalley

Jeffory L. Smalley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10455731
    Abstract: Embodiments herein relate to hydraulic bladders to provide a force against an integrated circuit package to be located between the hydraulic bladder and a system board. In various embodiments, a hydraulic force generator may include a block to be coupled with a system board and a hydraulic bladder to be located between the block and the system board, where the hydraulic bladder, in response to pressurization, is to provide a force against an integrated circuit package to be located between the hydraulic bladder and the system board. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: October 22, 2019
    Assignee: Intel Corporation
    Inventors: Ralph W. Jensen, Jeffory L. Smalley, Kevin J. Ceurter, Devdatta P. Kulkarni, Casey Winkel
  • Patent number: 10455685
    Abstract: An electronic device may include a circuit board, and the circuit board may include a dielectric material. A socket may be coupled to a first side of the circuit board, and the socket may be configured to receive a semiconductor package. A backing plate may be positioned on a second side of the circuit board. A spacer may be positioned between the backing plate and the circuit board. The spacer may alter the profile of the socket to provide a curved profile to the socket. The spacer may displace a portion of the socket in a first direction, for instance when the spacer is coupled between the backing plate and the circuit board.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: October 22, 2019
    Assignee: Intel Corporation
    Inventors: Steven A. Klein, Kuang Liu, Thomas A. Boyd, Luis Gil Rangel, Muffadal Mukadem, Shelby A. Ferguson, Francis Toth, Jr., Eric Buddrius, Ralph V. Miele, Sriram Srinivasan, Jeffory L. Smalley
  • Publication number: 20190302857
    Abstract: A microprocessor loading mechanism, comprising a bolster plate surrounding an aperture, wherein the opening is to receive a microprocessor socket, one or more torsion bars coupled to the bolster plate, and a stud coupled to each of the one or more torsion bars, wherein each stud is to receive a nut to secure a microprocessor package to the microprocessor socket within the aperture and wherein each stud is secured to the bolster plate by each corresponding torsion bar.
    Type: Application
    Filed: March 30, 2018
    Publication date: October 3, 2019
    Applicant: INTEL CORPORATION
    Inventors: Eric W. Buddrius, Ralph V. Miele, Mohanraj Prabhugoud, David Shia, Jeffory L. Smalley
  • Patent number: 10418309
    Abstract: Described herein are microelectronics packages and methods for manufacturing the same. The microelectronics package may include a substrate, a first die, a gasket, and a thermal interface. The first die may be connected to the substrate. The gasket may be connected to the substrate and may encircle the first die to form a space between the first die and the gasket. The thermal interface material may be located within the space formed by the first die and the gasket.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: September 17, 2019
    Assignee: Intel Corporation
    Inventors: Bijoyraj Sahu, Thomas A. Boyd, Jeffory L. Smalley
  • Publication number: 20190182955
    Abstract: Electronic device package technology is disclosed. An electronic device package in accordance with the present disclosure can include a package substrate. The electronic device package can also include a processor mounted on the package substrate. Additionally, the electronic device package can include a memory socket mounted on the package substrate and operably coupled to the processor. The memory socket can be operable to removably couple with a memory module and facilitate electrical communication between the processor and the memory module. A memory module can include a plurality of printed circuit boards (PCBs). Each PCB can have a bottom edge and a plurality of contact pads located about the bottom edge. Additionally, the memory module can include a memory device mounted on at least one of the plurality of PCBs and electrically connected to at least one of the pluralities of contact pads to facilitate electrically coupling the memory module with an external electronic component, such as a processor.
    Type: Application
    Filed: December 13, 2017
    Publication date: June 13, 2019
    Applicant: Intel Corporation
    Inventors: Gregorio R. Murtagian, Kuang C. Liu, Sriram Srinivasan, Jeffory L. Smalley, Zhichao Zhang
  • Publication number: 20190067158
    Abstract: An apparatus including a primary device and at least one secondary device coupled in a planar array to a substrate; a first passive heat exchanger disposed on the primary device and having an opening over an area corresponding to the at least one secondary device; a second passive heat exchanger disposed on the at least one secondary device; at least one first spring operable to apply a force to the first heat exchanger in a direction of the primary device; and at least one second spring operable to apply a force to the second heat exchanger in the direction of the secondary device. A method including placing a passive heat exchanger on a multi-chip package, and deflecting a spring to apply a force in a direction of an at least one secondary device on the package.
    Type: Application
    Filed: October 30, 2018
    Publication date: February 28, 2019
    Inventors: Jeffory L. SMALLEY, Susan F. SMITH, Mani PRAKASH, Tao LIU, Henry C. BOSAK, Harvey R. KOFSTAD, Almanzo T. ORTIZ
  • Patent number: 10211120
    Abstract: A rework grid array interposer with direct power is described. The interposer has a foundation layer mountable between a motherboard and a package. A heater is embedded in the foundation layer to provide local heat to reflow solder to enable at least one of attachment or detachment of the package. A connector is mounted on the foundation layer and coupled to the heater and to the package to provide a connection path directly with the power supply and not via the motherboard. One type of interposer interfaces with a package having a solderable extension. Another interposer has a plurality of heater zones embedded in the foundation layer.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: February 19, 2019
    Assignee: Intel Corporation
    Inventors: Russell S. Aoki, Jonathan W. Thibado, Jeffory L. Smalley, David J. Llapitan, Thomas A. Boyd, Harvey R. Kofstad, Dimitrios Ziakas, Hongfei Yan
  • Patent number: 10205292
    Abstract: Embodiments of the present disclosure are directed towards socket contact techniques and configurations. In one embodiment, an apparatus may include a socket substrate having a first side and a second side disposed opposite to the first side, an opening formed through the socket substrate, an electrical contact disposed in the opening and configured to route electrical signals between the first side and the second side of the socket substrate, the electrical contact having a cantilever portion that extends beyond the first side, wherein the first side and surfaces of the socket substrate in the opening are plated with a metal. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: February 12, 2019
    Assignee: INTEL CORPORATION
    Inventors: Dhanya Athreya, Gaurav Chawla, Kemal Aygun, Glen P. Gordon, Sarah M. Canny, Jeffory L. Smalley, Srikant Nekkanty, Michael Garcia, Joshua D. Heppner
  • Publication number: 20190044264
    Abstract: Apparatuses and systems associated with power provision for packages mounted to a printed circuit board are disclosed herein. In embodiments, a socket arrangement may include a header and a first bus bar, wherein the first bus bar is to extend from the header adjacent to the PCB, and is to electrically couple to a power supply contact of a component package and to a power supply connection within a proximity of a power source, wherein a power output of the power source is electrically coupled to the power supply connection. The socket arrangement may further include a second bus bar, wherein the second bus bar is to extend from the header adjacent to the PCB, and is to electrically couple to a ground contact of the component package and a ground connection within the proximity of the power source. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: January 12, 2018
    Publication date: February 7, 2019
    Inventors: BRIAN D. ASPNES, JEFFORY L. SMALLEY, WEIMIN SHI
  • Publication number: 20180352649
    Abstract: An apparatus is provided which comprises: a processor substrate extended away from a processor die, wherein the processor substrate has at least one signal interface which is connectable to a connector; and an interposer coupled to the processor substrate and a motherboard. Described is an apparatus which comprises: a processor substrate extended away from a processor die, wherein the processor substrate has at least one signal interface; and a motherboard coupled to the processor substrate, wherein the motherboard is configured to have a hole which is large enough to place a connector at least partially in it to couple with the at least one signal interface.
    Type: Application
    Filed: June 2, 2016
    Publication date: December 6, 2018
    Applicant: Intel Corporation
    Inventors: Russell S. Aoki, Jeffory L. Smalley, Jonathan W. Thibado
  • Patent number: 10141241
    Abstract: An apparatus including a primary device and at least one secondary device coupled in a planar array to a substrate; a first passive heat exchanger disposed on the primary device and having an opening over an area corresponding to the at least one secondary device; a second passive heat exchanger disposed on the at least one secondary device; at least one first spring operable to apply a force to the first heat exchanger in a direction of the primary device; and at least one second spring operable to apply a force to the second heat exchanger in the direction of the secondary device. A method including placing a passive heat exchanger on a multi-chip package, and deflecting a spring to apply a force in a direction of an at least one secondary device on the package.
    Type: Grant
    Filed: September 27, 2014
    Date of Patent: November 27, 2018
    Assignee: Intel Corporation
    Inventors: Jeffory L. Smalley, Susan F. Smith, Mani Prakash, Tao Liu, Henry C. Bosak, Harvey R. Kofstad, Almanzo T. Ortiz
  • Publication number: 20180263137
    Abstract: Embodiments herein relate to hydraulic bladders to provide a force against an integrated circuit package to be located between the hydraulic bladder and a system board. In various embodiments, a hydraulic force generator may include a block to be coupled with a system board and a hydraulic bladder to be located between the block and the system board, where the hydraulic bladder, in response to pressurization, is to provide a force against an integrated circuit package to be located between the hydraulic bladder and the system board. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 13, 2017
    Publication date: September 13, 2018
    Inventors: RALPH W. JENSEN, JEFFORY L. SMALLEY, KEVIN J. CEURTER, DEVDATTA P. KULKARNI, CASEY WINKEL
  • Patent number: 9935033
    Abstract: An apparatus including a primary device and at least one secondary device coupled in a planar array to a substrate; a first heat exchanger disposed on the primary device and having an opening over an area corresponding to the at least one secondary device; a second heat exchanger disposed in the opening on the at least one secondary device; at least one heat pipe coupled to the first heat exchanger and the second heat exchanger. A method including placing a heat exchanger on a multi-chip package, the heat exchanger including a first portion, a second portion and at least one heat pipe coupled to the first portion and the second portion; and coupling the heat exchanger to the multi-chip package.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: April 3, 2018
    Assignee: Intel Corporation
    Inventors: Susan F. Smith, Jeffory L. Smalley, Mani Prakash, Thu Huynh
  • Publication number: 20180040536
    Abstract: An apparatus including a primary device and at least one secondary device coupled to a substrate; a heat exchanger disposed on the primary device and on the at least one secondary device, wherein the heat exchanger includes at least one portion disposed over an area corresponding to the primary device or the at least one second device including a deflectable surface; and at least one thermally conductive conduit coupled to the heat exchanger. A method including placing a heat exchanger on a multi-chip package, the heat exchanger including the heat exchanger including at least one floating section operable to move in a direction toward or away from at least one of the plurality of dice and at least one thermally conductive conduit disposed in a channel of the heat exchanger and connected to the at least one floating section; and coupling the heat exchanger to the multi-chip package.
    Type: Application
    Filed: October 18, 2017
    Publication date: February 8, 2018
    Inventors: Jeffory L. Smalley, Susan F. Smith, Thu Huynh, Mani Prakash
  • Publication number: 20180019558
    Abstract: Embodiments of the present disclosure are directed towards socket contact techniques and configurations. In one embodiment, an apparatus may include a socket substrate having a first side and a second side disposed opposite to the first side, an opening formed through the socket substrate, an electrical contact disposed in the opening and configured to route electrical signals between the first side and the second side of the socket substrate, the electrical contact having a cantilever portion that extends beyond the first side, wherein the first side and surfaces of the socket substrate in the opening are plated with a metal. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 26, 2017
    Publication date: January 18, 2018
    Inventors: Dhanya Athreya, Gaurav Chawla, Kemal Aygun, Glen P. Gordon, Sarah M. Canny, Jeffory L. Smalley, Srikant Nekkanty, Michael Garcia, Joshua D. Heppner
  • Publication number: 20180007791
    Abstract: Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.
    Type: Application
    Filed: September 12, 2017
    Publication date: January 4, 2018
    Inventors: Mani Prakash, Thomas T. Holden, Jeffory L. Smalley, Ram S. Viswanath, Bassam N. Coury, Dimitrios Ziakas, Chong J. Zhao, Jonathan W. Thibado, Gregorio R. Murtagian, Kuang C. Liu, Rajasekaran Swaminathan, Zhichao Zhang, John M. Lynch, David J. Llapitan, Sanka Ganesan, Xiang Li, George Vergis
  • Patent number: 9859636
    Abstract: An example apparatus for connecting linear edge cards includes a housing to hold at least one set of conductive contacts facing perpendicularly towards a mating plane. The apparatus further includes an activator bar coupled to the housing, the activator bar to hold two parts of the housing apart via two opposing normal forces. The apparatus also includes a contact load spring coupled to the housing, the contact load spring to apply two forces parallel to the direction of the conductive contacts and against the two opposing normal forces of the activator bar. The apparatus further includes an ejector spring coupled to the contact load spring and the activator bar. The ejector spring is to apply a force perpendicular to the two opposing normal forces of the activator bar and in a direction of an opening of the housing.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: January 2, 2018
    Assignee: Intel Corporation
    Inventors: Thomas A. Boyd, Jeffory L. Smalley, Russell S. Aoki, Karumbu Meyyappan
  • Patent number: 9848510
    Abstract: Embodiments of the present disclosure are directed towards a socket loading element and associated techniques and configurations. In one embodiment, an apparatus may include a loading element configured to transfer a compressive load from a heat spreader to a socket assembly, wherein the loading element is configured to form a perimeter around a die when the loading element is coupled with an interposer disposed between the die and the socket assembly and wherein the loading element includes an opening configured to accommodate the die. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: December 19, 2017
    Assignee: Intel Corporation
    Inventors: Vijaykumar Krithivasan, Jeffory L. Smalley, David J. Llapitan, Gaurav Chawla, Mani Prakash, Susan F. Smith
  • Publication number: 20170354031
    Abstract: An apparatus is provided which comprises: a processor die; a processor substrate having a region extended away from the processor die, wherein the processor die is mounted on the processor substrate, wherein the extended region has at least one signal interface which is connectable to a top-side connector; and an interposer coupled to the processor substrate and a motherboard.
    Type: Application
    Filed: June 2, 2016
    Publication date: December 7, 2017
    Inventors: Russell S. Aoki, Jeffory L. Smalley, Jonathan W. Thibado
  • Patent number: 9832876
    Abstract: Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: November 28, 2017
    Assignee: Intel Corporation
    Inventors: Mani Prakash, Thomas T. Holden, Jeffory L. Smalley, Ram S. Viswanath, Bassam N. Coury, Dimitrios Ziakas, Chong J. Zhao, Jonathan W. Thibado, Gregorio R. Murtagian, Kuang C. Liu, Rajasekaran Swaminathan, Zhichao Zhang, John M. Lynch, David J. Llapitan, Sanka Ganesan, Xiang Li, George Vergis