Abstract: An antenna and antenna enclosure including a housing having a cylindrical first portion defining a hollow interior volume with an inner diameter, a cylindrical second portion defining a hollow interior portion having an inner diameter greater than the inner diameter of the first portion, and a disk disposed inside the second portion and defining a central hole. A rod is disposed in and extends through the central hole of the disk and is captured in the hollow interior volume of the cylindrical first portion. The rod defines a central opening and abuts an inner surface of the disk. A wire is arranged inside the central opening, and a cap covers the hollow interior of the cylindrical portion and engages the housing. A circuit board for the antenna is disposed on underside of the cap and connects to the wire.

Abstract: Disclosed herein is a transportable bio-cement comprising a desiccated microorganism package; where the microorganism package comprises one or more microorganisms; a first binder, where the first binder is produced by the microorganism; and where the microorganism has protected itself by a layer of the first binder; where the transportable bio-cement is devoid of moisture. Disclosed herein too is a method of manufacturing a transportable dry composition comprising blending together a microorganism package; a nutrient; and a liquid; activating the microorganism package to produce a first binder; subjecting the microorganism package to desiccation to form a transportable bio-cement; and blending the transportable bio-cement with an aggregate to form a bio-concrete; where the aggregate comprises a substrate, a second binder, and a liquid.

Abstract: An AMI/AMR in-ground meter box, including first and second side panels, each having an interior side and an exterior side; and first and second end panels, each having an interior side and an exterior side; wherein each of said side panels and end panels include a generally rectangular planar portion having a top edge, a bottom edge, a first interlocking end having a plurality of male elements and female slots, an arcuate second end having a 90-degree bend which forms a corner of the assembled meter box and terminating in an interlocking end having a plurality of male elements and female slots configured to interlock with paired male elements and female slots in said first interlocking end.

Abstract: New formulations of clomazone are provided, as well as new methods for making formulations of clomazone. The new formulations provide improved efficacy, decreased volatility, and/or increased loading of clomazone over the clomazone formulations in the prior art.

Abstract: An assembly includes: a) a housing comprising a floor, a ceiling, a rear wall, a front wall, and opposed side walls that define a cavity, wherein the side walls include illuminable informational markings; an antenna; c) a radio residing in the cavity of the housing connected with the antenna; and d) a power source attached to the radio; wherein the power source is employed to illuminate the informational markings.

Abstract: An electrical backshell that includes a strain relief having a flexible neck connected to a jacketed data cable proximate a terminal end of the data cable, and a cylindrical portion integral with said flexible neck; a base connector configured to accept and accommodate the terminal end of the data cable; a coupling nut configured to connect with said base connector and to engage said strain relief and to bring said cylindrical portion of said strain relief into sealing engagement with said base connector, wherein when assembled, said electrical backshell provides waterproof protection for electrical connectors in underground utility meter boxes.

Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.

Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.

Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.

Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.

Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.

Abstract: Techniques for using soft-barrier hints are described. An example includes a synchronous microthreading (SyMT) co-processor coupled to a logical processor to execute a plurality of microthreads, with each microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode, wherein the SyMT co-processor is further to support a soft-barrier hint instruction in code which when processed by a microthread is to pause execution of the microthread to be resumed based at least in part on a data structure having at least one entry, the entry to include an instruction pointer of the soft-barrier hint instruction and a count of microthreads that have encountered the soft-barrier hint instruction at the instruction pointer.

Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.

Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.

Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.

Abstract: An apparatus to facilitate acceleration of machine learning operations is disclosed. The apparatus comprises at least one processor to perform operations to implement a neural network and accelerator logic to perform communicatively coupled to the processor to perform compute operations for the neural network.

Abstract: An apparatus and method for performing efficient, adaptable tensor operations. For example, one embodiment of a processor comprises: front end circuitry to schedule matrix operations responsive to a matrix multiplication instruction; a plurality of lanes to perform parallel execution of the matrix operations, wherein a lane comprises an arithmetic logic unit to multiply a block of a first matrix with a block of a second matrix to generate a product and to accumulate the product with a block of a third matrix, and wherein the matrix blocks are to be stored in registers within the lane; and broadcast circuitry to broadcast one or more invariant matrix blocks to at least one of different registers within the lane and different registers across different lanes.

Abstract: An apparatus to facilitate acceleration of machine learning operations is disclosed. The apparatus comprises at least one processor to perform operations to implement a neural network and accelerator logic to perform communicatively coupled to the processor to perform compute operations for the neural network.

Abstract: An assembly includes: a) a housing comprising a floor, a ceiling, a rear wall, a front wall, and opposed side walls that define a cavity, wherein the side walls include illuminable informational markings; an antenna; c) a radio residing in the cavity of the housing connected with the antenna; and d) a power source attached to the radio; wherein the power source is employed to illuminate the informational markings.