Abstract: In one aspect, the invention includes a semiconductor processing method, comprising: a) providing a silicon nitride material having a surface; b) forming a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; and c) forming a photoresist over and against the barrier layer.

Abstract: In one aspect, the invention includes a method of forming a gated semiconductor assembly, comprising: a) forming a silicon nitride layer over and against a floating gate; and b) forming a control gate over the silicon nitride layer. In another aspect, the invention includes a method of forming a gated semiconductor assembly, comprising: a) forming a floating gate layer over a substrate; b) forming a silicon nitride layer over the floating gate layer, the silicon nitride layer comprising a first portion and a second portion elevationally displaced from the first portion, the first portion having a greater stoichiometric amount of silicon than the second portion; and c) forming a control gate over the silicon nitride layer.

Abstract: In one aspect, the invention includes a semiconductor processing method, comprising: a) providing a silicon nitride material having a surface; b) forming a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; and c) forming a photoresist over and against the barrier layer.

Abstract: In one aspect, the invention includes a semiconductor fabrication process, comprising: a) providing a substrate; b) forming a layer of silicon nitride over the substrate, the layer having a thickness; and c) enriching a portion of the thickness of the silicon nitride layer with silicon, the portion comprising less than or equal to about 95% of the thickness of the layer of silicon nitride. In another aspect, the invention includes a semiconductor fabrication process, comprising: a) providing a substrate; b) forming a layer of silicon nitride over the substrate, the layer having a thickness; and c) increasing a refractive index of a first portion of the thickness of the silicon nitride layer relative to a refractive index of a second portion of the silicon nitride layer, the first portion comprising less than or equal to about 95% of the thickness of the silicon nitride layer.

Abstract: In one aspect, the invention includes a semiconductor fabrication process, comprising: a) providing a substrate; b) forming a layer of silicon nitride over the substrate, the layer having a thickness; and c) enriching a portion of the thickness of the silicon nitride layer with silicon, the portion comprising less than or equal to about 95% of the thickness of the layer of silicon nitride. In another aspect, the invention includes a semiconductor fabrication process, comprising: a) providing a substrate; b) forming a layer of silicon nitride over the substrate, the layer having a thickness; and c) increasing a refractive index of a first portion of the thickness of the silicon nitride layer relative to a refractive index of a second portion of the silicon nitride layer, the first portion comprising less than or equal to about 95% of the thickness of the silicon nitride layer.

Abstract: The invention includes a method of forming a gated semiconductor assembly. A first transistor gate layer is formed over a substrate. A silicon nitride layer is formed over the first transistor gate layer. The silicon nitride layer comprises a first portion and a second portion elevationally displaced above the first portion. The first portion has less electrical resistance than the second portion and a different stoichiometric composition than the second portion. The first portion is physically against the second portion. A second transistor gate layer is formed over the silicon nitride layer.

Abstract: The invention pertains to semiconductor circuit components and capacitors, and to methods of forming capacitors and semiconductor circuit components. In one aspect, the invention includes a method of forming a dielectric layer comprising: a) forming a first tantalum-comprising layer; and b) forming a second tantalum-comprising layer over the first tantalum-comprising layer, the second tantalum-comprising layer comprising nitrogen. In another aspect, the invention includes a method of forming a capacitor comprising: a) forming a first capacitor plate; b) forming a first layer over the first capacitor plate, the first layer comprising tantalum and oxygen; c) annealing the first layer in the presence of an ambient comprising a nitrogen-comprising gas containing at least one compound selected from a group consisting of ammonia, hydrazine and hydrazoic acid; the annealing forming a second layer over the first layer; and d) forming a second capacitor plate over the second layer.

Abstract: The invention encompasses methods of processing internal surfaces of a chemical vapor deposition reactor. In one implementation, material is deposited over internal surfaces of a chemical vapor deposition reactor while processing semiconductor substrates therein. The deposited material is treated with atomic oxygen. After the treating, at least some of the deposited material is etched from the reactor internal surfaces. In one embodiment, first etching is conducted of some of the deposited material from the reactor internal surfaces. After the first etching, remaining deposited material is treated with atomic oxygen. After the treating, second etching is conducted of at least some of the remaining deposited material from the reactor internal surfaces. In one embodiment, the deposited material is first treated with atomic oxygen. After the first treating, first etching is conducted of some of the deposited material from the reactor internal surfaces.

Abstract: The invention includes buried bit line memory circuitry, methods of forming buried bit line memory circuitry, and semiconductor processing methods of forming conductive lines. In but one implementation, a semiconductor processing method of forming a conductive line includes forming a silicon comprising region over a substrate. A TiNx comprising layer is deposited over the silicon comprising region, where “x” is greater than 0 and less than 1. The TiNx comprising layer is annealed in a nitrogen containing atmosphere effective to transform at least an outermost portion of the TiNx layer over the silicon comprising region to TiN. After the annealing, an elemental tungsten comprising layer is deposited on the TiN and at least the elemental tungsten comprising layer, the TiN, and any remaining TiNx layer is patterned into conductive line. In one implementation, a method such as the above is utilized in the fabrication of buried bit line memory circuitry.

Abstract: Silicon nitride layers, having thicknesses of 100 angstroms or less, are formed using chemical vapor deposition (CVD). Higher pressure and lower temperature deposition regimes are used to provide more uniform step coverage on complex topographies, such as hemispherical grain polysilicon. In one embodiment, a hot wall batch CVD processing apparatus utilizes a processing chamber pressure of at least as high as approximately 500 mTorr to deposit such films. In a second embodiment, a single wafer cold wall CVD processing apparatus utilizes a processing chamber pressure of approximately 1 to 600 Torr to deposit such films. The temperature range used to process such films is approximately 400 to 700 degrees Celsius. A mixture of ammonia (NH3) and a silane gas, such as dichlorosilane (DCS), are reacted in any type of CVD apparatus to produce the films.

Abstract: A capacitor has a tantalum oxynitride film. One method for making the film comprises forming a bottom plate electrode and then forming a tantalum oxide film on the bottom plate electrode. Nitrogen is introduced to form a tantalum oxynitride film. A top plate electrode is formed on the tantalum oxynitride film.

Abstract: A capacitor has a tantalum oxynitride film. One method for making the film comprises forming a bottom plate electrode and then forming a tantalum oxide film on the bottom plate electrode. Nitrogen is introduced to form a tantalum oxynitride film. A top plate electrode is formed on the tantalum oxynitride film.

Abstract: A high dielectric constant (DC) capacitive dielectric film is fabricated in a capacitor structure using relatively high pressure surface treatments. After forming the DC capacitive dielectric film on a supporting bottom plate electrode structure, a surface treatment comprising oxidation, at a pressure of at least approximately one atmosphere and temperatures of approximately at least 200 degrees Celsius densities/conditions the HDC capacitive dielectric film. When using a polysilicon, crystalline silicon, hemispherical grain polysilicon, germanium, or silicon-germanium bottom plate electrode, a relatively high pressure surface treatment, comprising rapid thermal nitridation or oxidation, is used after forming the bottom plate electrode, forming a diffusion barrier layer in a controlled manner.

Abstract: The invention includes a semiconductor processing method. A first material comprising silicon and nitrogen is formed. A second material is formed over the first material, and the second material comprises silicon and less nitrogen, by atom percent, than the first material. An imagable material is formed on the second material, and patterned. A pattern is then transferred from the patterned imagable material to the first and second materials. The invention also includes a structure comprising a first layer of silicon nitride over a substrate, and a second layer on the first layer. The second layer comprises silicon and is free of nitrogen. The structure further comprises a third layer consisting essentially of imagable material on the second layer.

Abstract: The invention includes a semiconductor processing method. A first material comprising silicon and nitrogen is formed. A second material is formed over the first material, and the second material comprises silicon and less nitrogen, by atom percent, than the first material. An imagable material is formed on the second material, and patterned. A pattern is then transferred from the patterned imagable material to the first and second materials. The invention also includes a structure comprising a first layer of silicon nitride over a substrate, and a second layer on the first layer. The second layer comprises silicon and is free of nitrogen. The structure further comprises a third layer consisting essentially of imagable material on the second layer.

Abstract: The invention includes a semiconductor processing method. A first material comprising silicon and nitrogen is formed. A second material is formed over the first material, and the second material comprises silicon and less nitrogen, by atom percent, than the first material. An imagable material is formed on the second material, and patterned. A pattern is then transferred from the patterned imagable material to the first and second materials. The invention also includes a structure comprising a first layer of silicon nitride over a substrate, and a second layer on the first layer. The second layer comprises silicon and is free of nitrogen. The structure further comprises a third layer consisting essentially of imagable material on the second layer.

Abstract: The invention includes a semiconductor processing method. A first material comprising silicon and nitrogen is formed. A second material is formed over the first material, and the second material comprises silicon and less nitrogen, by atom percent, than the first material. An imagable material is formed on the second material, and patterned. A pattern is then transferred from the patterned imagable material to the first and second materials. The invention also includes a structure comprising a first layer of silicon nitride over a substrate, and a second layer on the first layer. The second layer comprises silicon and is free of nitrogen. The structure further comprises a third layer consisting essentially of imagable material on the second layer.

Abstract: A capacitor has a tantalum oxynitride film. One method for making the film comprises forming a bottom plate electrode and then forming a tantalum oxide film on the bottom plate electrode. Nitrogen is introduced to form a tantalum oxynitride film. A top plate electrode is formed on the tantalum oxynitride film.

Abstract: The invention includes a semiconductor processing method. A first material comprising silicon and nitrogen is formed. A second material is formed over the first material, and the second material comprises silicon and less nitrogen, by atom percent, than the first material. An imagable material is formed on the second material, and patterned. A pattern is then transferred from the patterned imagable material to the first and second materials. The invention also includes a structure comprising a first layer of silicon nitride over a substrate, and a second layer on the first layer. The second layer comprises silicon and is free of nitrogen. The structure further comprises a third layer consisting essentially of imagable material on the second layer.

Abstract: The invention includes buried bit line memory circuitry, methods of forming buried bit line memory circuitry, and semiconductor processing methods of forming conductive lines. In but one implementation, a semiconductor processing method of forming a conductive line includes forming a silicon comprising region over a substrate. A TiNx comprising layer is deposited over the silicon comprising region, where “x” is greater than 0 and less than 1. The TiNx comprising layer is annealed in a nitrogen containing atmosphere effective to transform at least an outermost portion of the TiNx layer over the silicon comprising region to TiN. After the annealing, an elemental tungsten comprising layer is deposited on the TiN and at least the elemental tungsten comprising layer, the TiN, and any remaining TiNx layer is patterned into conductive line. In one implementation, a method such as the above is utilized in the fabrication of buried bit line memory circuitry.