Abstract: An embodiment of a packaged radio frequency (RF) amplifier device includes a transistor and an inverse class-F circuit configured to harmonically terminate the device. The transistor has a control terminal and first and second current carrying terminals. The control terminal is coupled to an input lead of the device, and the first current carrying terminal is coupled to a voltage reference. The inverse class-F circuit is coupled between the second current carrying terminal and an output lead. The inverse class-F circuit includes a shunt circuit coupled between a cold point node and the voltage reference, where the cold point node corresponds to a second harmonic frequency cold point for the device. The shunt circuit adds a shunt negative susceptance at a fundamental frequency F0 to the inverse class-F circuit.

Abstract: An embodiment of a packaged radio frequency (RF) amplifier device includes a transistor and an inverse class-F circuit configured to harmonically terminate the device. The transistor has a control terminal and first and second current carrying terminals. The control terminal is coupled to an input lead of the device, and the first current carrying terminal is coupled to a voltage reference. The inverse class-F circuit is coupled between the second current carrying terminal and an output lead. The inverse class-F circuit includes a shunt circuit coupled between a cold point node and the voltage reference, where the cold point node corresponds to a second harmonic frequency cold point for the device. The shunt circuit adds a shunt negative susceptance at a fundamental frequency F0 to the inverse class-F circuit.

Abstract: A method and apparatus for a power amplifier module is described. The module includes a power amplifier and a power supply modulator coupled to the power amplifier. In addition, the module includes an inverter coupled between the power amplifier and the power supply modulator. The inverter provides a predistorted signal to the power amplifier to cancel distortion in the power amplifier provided by the power supply modulator. In addition, the module can include a driver coupled between the power amplifier and the inverter wherein the driver supplies the predistorted signal to the power amplifier.

Abstract: A method and apparatus for a power amplifier module is described. The module includes a power amplifier and a power supply modulator coupled to the power amplifier. In addition, the module includes an inverter coupled between the power amplifier and the power supply modulator. The inverter provides a predistorted signal to the power amplifier to cancel distortion in the power amplifier provided by the power supply modulator. In addition, the module can include a driver coupled between the power amplifier and the inverter wherein the driver supplies the predistorted signal to the power amplifier.

Abstract: The application discloses a method and apparatus for adjusting internal load impedances, by section, at feed points present on a distributed amplifier's output transmission line. The method includes determining a summing-point load impedance (Zx) at an off-chip output transmission line of the distributed amplifier. The method further includes determining a driving-point load impedance (Zd) at an output of an on-chip power transistor. The driving-point load impedance diverges and disperses over frequency from that summing-point load impedance due to reactance of at least one on-chip component coupled to the output of the on-chip power transistor. The method then includes determining and providing an offset to summing-point load impedance (Zx) based on the driving-point load impedance (Zd) such that the driving-point load impedance (Zd) converges to the summing-point load impedance (Zx) of that distributed amplifier section.

Abstract: The application discloses a method and apparatus for adjusting internal load impedances, by section, at feed points present on a distributed amplifier's output transmission line. The method includes determining a summing-point load impedance (Zx) at an off-chip output transmission line of the distributed amplifier. The method further includes determining a driving-point load impedance (Zd) at an output of an on-chip power transistor. The driving-point load impedance diverges and disperses over frequency from that summing-point load impedance due to reactance of at least one on-chip component coupled to the output of the on-chip power transistor. The method then includes determining and providing an offset to summing-point load impedance (Zx) based on the driving-point load impedance (Zd) such that the driving-point load impedance (Zd) converges to the summing-point load impedance (Zx) of that distributed amplifier section.

Abstract: Power amplifier (PA) apparatus that includes: a PA device operating at a fundamental frequency and having a maximum operating frequency that is higher than the fundamental frequency, an output current having a fundamental component at the fundamental frequency and a plurality of harmonic components at different harmonic frequencies of the fundamental frequency, and an output voltage based on the output current; a first matching circuit coupled to the PA device and corresponding to the fundamental component; and a second matching circuit coupled between the PA device and the first matching circuit and corresponding to at least one of the harmonic components, wherein the first and second matching circuits maintain the PA output voltage at a value that is no more than a predetermined maximum value, which is less than a breakdown voltage for the PA device.

Abstract: Power amplifier (PA) apparatus that includes: a PA device operating at a fundamental frequency and having a maximum operating frequency that is higher than the fundamental frequency, an output current having a fundamental component at the fundamental frequency and a plurality of harmonic components at different harmonic frequencies of the fundamental frequency, and an output voltage based on the output current; a first matching circuit coupled to the PA device and corresponding to the fundamental component; and a second matching circuit coupled between the PA device and the first matching circuit and corresponding to at least one of the harmonic components, wherein the first and second matching circuits maintain the PA output voltage at a value that is no more than a predetermined maximum value, which is less than a breakdown voltage for the PA device.

Abstract: A non-polarized laser trim chip stub in accordance with the invention includes a trimmable top conductor (12) capable of being trimmed to alter the electrical properties of the chip stub, a bottom conductor (58) having at least a first conductive portion (68) and a second conductive portion (72), a dielectric (44) separating said top conductor from said bottom conductor, and conductive passages (42) electrically connecting the top conductor or a portion thereof to the bottom conductor or a portion thereof. In alternate embodiments, the non-polarized laser trim chip stub's top conductor (102) is separated into a trimmable stub portion (110) and an end portion (112), and the bottom conductor (150) may be separated into three conductive portions (160, 162 and 164) to allow for the middle portion (162) to be used as a heat sink to aid in the dissipation of heat generated during high power applications.