Patents by Inventor Jeffrey A. Gleason

Jeffrey A. Gleason has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7626777
    Abstract: A method and apparatus for detecting signal peaks caused by a thermal asperity event in a magnetic recording media to reduce data reading errors introduced by the thermal asperity event. A common mode voltage is determined for differential signals representing data bits read from the magnetic recording media and a threshold voltage produced responsive to the common mode voltage. A comparator determines if either of the differential signals exceeds the threshold voltage, thereby indicating the occurrence of a thermal asperity event.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: December 1, 2009
    Assignee: Agere Systems Inc.
    Inventors: Arvind R. Aemireddy, Ronen Malka, Jeffrey A. Gleason, Scott M. O'Brien
  • Publication number: 20090073297
    Abstract: Methods for forming conductors and global bus configurations for reducing an interference signal from electromagnetic interference (EMI) source are provided. First and second conductor lines are formed on an integrated circuit in a twisted pair configuration. A differential amplifier is formed on the integrated circuit and coupled to each of the first and second conductor lines. The first and second signals are respectively transmitted through the first and second conductor lines and are modified by the interference signal. The modified first and second signals are differentially amplified by the differential amplifier so that the interference signal is substantially cancelled.
    Type: Application
    Filed: September 17, 2007
    Publication date: March 19, 2009
    Applicant: Micron Technology, Inc.
    Inventors: Taehee Cho, Jeffrey Gleason, Espen Olsen, Kwang-bo (Austin) Cho, Suat Utku Ay
  • Patent number: 7425867
    Abstract: A differential input/differential output converter circuit. The circuit comprises differential complementary input modules each comprising cross-coupled devices for biasing current mirror masters to a condition that increases the operating speed in response to a transition in the differential input signals. Certain current mirror masters are biased to a strong threshold condition and other current mirror masters are biased to a weak threshold condition responsive to a state of the differential input signals. According to another embodiment, the converter circuit further comprises a boost circuit capacitively coupled to the converter circuit for providing further speed improvements.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: September 16, 2008
    Assignee: Agere Systems Inc.
    Inventors: Arvind R. Aemireddy, Robert J. Wimmer, Cameron Carroll Rabe, Jeffrey A. Gleason
  • Publication number: 20080062551
    Abstract: An apparatus and method for determining a head parameter value (e.g., head resistance) of a resistive head. A test head current is supplied to the head during a head parameter measurement interval using the same current sources that supply a bias current to the head during an operating (read operation) interval. The determined head parameter value is latched for use in setting the control loop gain for a control loop that controls the current sources during the operating interval.
    Type: Application
    Filed: September 13, 2006
    Publication date: March 13, 2008
    Inventors: Daniel J. Dolan, Hao Fang, Jeffrey A. Gleason, Ross S. Wilson
  • Patent number: 7339760
    Abstract: A preamplifier circuit is connected to a transducing head, and has integrated bias circuitry and offset recovery circuitry. The offset recovery circuitry is activated in response to a transition from write mode to read more to provide an output signal representative of a signal across the transducing head. The bias circuitry is driven by the output signal of the offset recovery circuitry to bias the transducing head.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: March 4, 2008
    Assignee: Agere Systems Inc.
    Inventors: Jeffrey A. Gleason, John D. Leighton, Scott M. O'Brien
  • Publication number: 20070075688
    Abstract: A differential input/differential output converter circuit. The circuit comprises differential complementary input modules each comprising cross-coupled devices for biasing current mirror masters to a condition that increases the operating speed in response to a transition in the differential input signals. Certain current mirror masters are biased to a strong threshold condition and other current mirror masters are biased to a weak threshold condition responsive to a state of the differential input signals. According to another embodiment, the converter circuit further comprises a boost circuit capacitively coupled to the converter circuit for providing further speed improvements.
    Type: Application
    Filed: September 30, 2005
    Publication date: April 5, 2007
    Inventors: Arvind Aemireddy, Robert Wimmer, Cameron Rabe, Jeffrey Gleason
  • Publication number: 20070070534
    Abstract: A method and apparatus for detecting signal peaks caused by a thermal asperity event in a magnetic recording media to reduce data reading errors introduced by the thermal asperity event. A common mode voltage is determined for differential signals representing data bits read from the magnetic recording media and a threshold voltage produced responsive to the common mode voltage. A comparator determines if either of the differential signals exceeds the threshold voltage, thereby indicating the occurrence of a thermal asperity event.
    Type: Application
    Filed: September 23, 2005
    Publication date: March 29, 2007
    Inventors: Arvind Aemireddy, Ronen Malka, Jeffrey Gleason, Scott O'Brien
  • Publication number: 20060267582
    Abstract: An apparatus and method for determining a resistance of a magneto-resistive head. A current drawn by the head, in response to a fixed bias voltage across the head, is converted to a zero temperature coefficient current such that when supplied to a resistor connected to an input terminal of a comparator the effects of variations in the resistance value are avoided. An output signal of the comparator indicates the resistance of the magneto-resistive head.
    Type: Application
    Filed: May 27, 2005
    Publication date: November 30, 2006
    Inventors: Scott O'Brien, Michael Straub, Jeffrey Gleason, Shubha Bommalingaiahnapallya, Nameeta Krenz, Arvind Aemireddy
  • Publication number: 20060152838
    Abstract: A recording system employing a magneto-resistive (MR) element senses a resistance value of the MR element and generates one or more MR resistance (MRR) signal values based on the sensed MR element resistance value. The MRR signal values might be, for example, current or voltage values proportional or inversely proportional to the MR element resistance value. The MRR signal values might be employed to control one or more of: i) a unity gain bandwidth of a bias loop for the MR element, ii) an MR read head preamplifier low corner frequency, and iii) a slew rate across the MR element.
    Type: Application
    Filed: January 13, 2005
    Publication date: July 13, 2006
    Inventors: David Fitzgerald, Jeffrey Gleason, James Howley, Scott O'Brien, Michael Straub
  • Publication number: 20050168860
    Abstract: A preamplifier circuit is connected to a transducing head, and has integrated bias circuitry and offset recovery circuitry. The offset recovery circuitry is activated in response to a transition from write mode to read more to provide an output signal representative of a signal across the transducing head. The bias circuitry is driven by the output signal of the offset recovery circuitry to bias the transducing head.
    Type: Application
    Filed: September 30, 2004
    Publication date: August 4, 2005
    Inventors: Jeffrey Gleason, John Leighton, Scott O'Brien
  • Publication number: 20050058115
    Abstract: A communication system is dynamically configured to use some or all of the communication channel bandwidth. Regions of the communication channel are prioritized, and bandwidth is allocated in accordance with priorities and requested data rate.
    Type: Application
    Filed: October 4, 2004
    Publication date: March 17, 2005
    Inventors: Howard Levin, Kenneth Cavanaugh, Jeffrey Gleason, Peter Molnar
  • Patent number: 5278700
    Abstract: An amplifier is compensated for variations in element values. A trim signal is generated based on element values of filter elements of a filter in the amplifier. An RC product in the amplifier is controlled based on the trim signal. The RC product corresponds to a product of a dynamic resistance value of a dynamic resistance element in the filter in the amplifier, and a capacitance value of capacitive elements in the filter. The RC product also determines a pole position of the amplifier. Gain in the amplifier is controlled based on the trim signal so that a desired gain is maintained.
    Type: Grant
    Filed: January 19, 1993
    Date of Patent: January 11, 1994
    Assignee: VTC Inc.
    Inventors: David E. Sutliff, Jeffrey A. Gleason
  • Patent number: 5227737
    Abstract: An amplifier is compensated for variations in element values. A trim signal is generated based on element values of filter elements of a filter in the amplifier. An RC product in the amplifier is controlled based on the trim signal. The RC product corresponds to a product of a dynamic resistance value of a dynamic resistance element in the filter in the amplifier, and a capacitance value of capacitive elements in the filter. The RC product also determines a pole position of the amplifier. Gain in the amplifier is controlled based on the trim signal so that a desired gain is maintained.
    Type: Grant
    Filed: December 5, 1990
    Date of Patent: July 13, 1993
    Assignee: VTC Inc.
    Inventors: David E. Sutliff, Jeffrey A. Gleason
  • Patent number: 4728902
    Abstract: A bipolar integrated circuit amplifier with a cascode stage has an emitter follower biasing circuit which provides a bias voltage to the cascode stage. The cascode amplifier stage is stabilized by providing a stabilization capacitance across the base-collector junction of the emitter follower in the biasing circuit.
    Type: Grant
    Filed: September 8, 1986
    Date of Patent: March 1, 1988
    Assignee: VTC Incorporated
    Inventors: Jeffrey Gleason, Richard E. Hester