Patents by Inventor Jeffrey A. Hedrick
Jeffrey A. Hedrick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190105721Abstract: A rapidly detachable table for a host combination vertical-horizontal band saw that provides an enlarged work platform in the vertical cutting mode. The table employs a rapidly activated latching mechanism so that the table is quickly installed to operate in the enhanced vertical cutting mode and quickly removed to allow normal horizontal cutting operation. The portfolio of cuts that the saw can make is increased, as is the accuracy of the cuts in the vertical cutting mode.Type: ApplicationFiled: September 15, 2018Publication date: April 11, 2019Inventor: Jeffrey A. Hedrick
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Patent number: 10199516Abstract: Photovoltaic devices are formed by laser drilling vias through silicon substrates and, following surface preparation of the via sidewalls, plating a continuous, electrically conductive layer on the via sidewalls to electrically connect the emitter side of the cell with the back side of the cell. The electrically conductive layer can be formed on portions of a base emitter within the vias and on the back side of the substrate. Alternatively, the electrically conductive layer can be formed on a passivation layer on the via sidewalls and back side of the cell.Type: GrantFiled: July 8, 2017Date of Patent: February 5, 2019Assignee: International Business Machines CorporationInventors: Brett Caroline Baker-O'Neal, Shu-Yun Chong, John Michael Cotte, Ronald Dean Goldblatt, Jeffrey Hedrick, Qiang Huang, Susan Huang, Laura Louise Kosbar, Rob Steeman, Roland Yudadibrata Utama
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Publication number: 20170309760Abstract: Photovoltaic devices are formed by laser drilling vias through silicon substrates and, following surface preparation of the via sidewalls, plating a continuous, electrically conductive layer on the via sidewalls to electrically connect the emitter side of the cell with the back side of the cell. The electrically conductive layer can be formed on portions of a base emitter within the vias and on the back side of the substrate. Alternatively, the electrically conductive layer can be formed on a passivation layer on the via sidewalls and back side of the cell.Type: ApplicationFiled: July 8, 2017Publication date: October 26, 2017Inventors: Brett Caroline Baker-O'Neal, Shu-Yun Chong, John Michael Cotte, Ronald Dean Goldblatt, Jeffrey Hedrick, Qiang Huang, Susan Huang, Laura Louise Kosbar, Rob Steeman, Roland Yudadibrata Utama
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Patent number: 9716192Abstract: Photovoltaic devices are formed by laser drilling vias through silicon substrates and, following surface preparation of the via sidewalls, plating a continuous, electrically conductive layer on the via sidewalls to electrically connect the emitter side of the cell with the back side of the cell. The electrically conductive layer can be formed on portions of a base emitter within the vias and on the back side of the substrate. Alternatively, the electrically conductive layer can be formed on a passivation layer on the via sidewalls and back side of the cell.Type: GrantFiled: March 19, 2015Date of Patent: July 25, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brett Caroline Baker-O'Neal, Shu-Yun Chong, John Michael Cotte, Ronald Dean Goldblatt, Jeffrey Hedrick, Qiang Huang, Susan Huang, Laura Louise Kosbar, Rob Steeman, Roland Yudadibrata Utama
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Publication number: 20150325716Abstract: Photovoltaic devices are formed with electroplated metal grids that are effectively adhered to the devices. Metal-rich silicides, such as nickel silicides, are formed on the devices by annealing. The metal used in the anneal exhibits low stress. Annealing may be conducted in ambient air followed by removal of oxide and excess metal from the metal-rich silicide. Laser patterning of the antireflective coating of the devices can be used to expose the emitter to form front grid contacts. Doping of the emitter in the patterned region can be increased during laser patterning. The ratio of the centerline to centerline pitch per laser width is controlled to ensure sufficient adhesion of subsequently plated busbars.Type: ApplicationFiled: March 19, 2015Publication date: November 12, 2015Inventors: Brett Caroline Baker-O'Neal, Shu-Yun Chong, John Michael Cotte, Ronald Dean Goldblatt, Jeffrey Hedrick, Qiang Huang, Susan Huang, Laura Louise Kosbar, Hwee Meng Lam, Christian Lavoie, Xiaoyan Shao, Rob Steeman
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Publication number: 20150280022Abstract: Photovoltaic devices are formed by laser drilling vias through silicon substrates and, following surface preparation of the via sidewalls, plating a continuous, electrically conductive layer on the via sidewalls to electrically connect the emitter side of the cell with the back side of the cell. The electrically conductive layer can be formed on portions of a base emitter within the vias and on the back side of the substrate. Alternatively, the electrically conductive layer can be formed on a passivation layer on the via sidewalls and back side of the cell.Type: ApplicationFiled: March 19, 2015Publication date: October 1, 2015Inventors: Brett Caroline Baker-O'Neal, Shu-Yun Chong, John Michael Cotte, Ronald Dean Goldblatt, Jeffrey Hedrick, Qiang Huang, Susan Huang, Laura Louise Kosbar, Rob Steeman, Roland Yudadibrata Utama
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Patent number: 8865502Abstract: The present disclosure provides a method of forming a back side surface field of a solar cell without utilizing screen printing. The method includes first forming a p-type dopant layer directly on the back side surface of the semiconductor substrate that includes a p/n junction utilizing an electrodeposition method. The p/n junction is defined as the interface that is formed between an n-type semiconductor portion of the substrate and an underlying p-type semiconductor portion of the substrate. The plated structure is then annealed to from a P++ back side surface field layer directly on the back side surface of the semiconductor substrate. Optionally, a metallic film can be electrodeposited on an exposed surface of the P++ back side surface layer.Type: GrantFiled: June 10, 2010Date of Patent: October 21, 2014Assignee: International Business Machines CorporationInventors: Kathryn C. Fisher, Nicholas C. M. Fuller, Satyavolu S. Papa Rao, Xiaoyan Shao, Jeffrey Hedrick
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Publication number: 20120325312Abstract: The present disclosure provides a method of forming a back side surface field of a solar cell without utilizing screen printing. The method includes first forming a p-type dopant layer directly on the back side surface of the semiconductor substrate that includes a p/n junction utilizing an electrodeposition method. The p/n junction is defined as the interface that is formed between an n-type semiconductor portion of the substrate and an underlying p-type semiconductor portion of the substrate. The plated structure is then annealed to from a P++ back side surface field layer directly on the back side surface of the semiconductor substrate. Optionally, a metallic film can be electrodeposited on an exposed surface of the P++ back side surface layer.Type: ApplicationFiled: September 6, 2012Publication date: December 27, 2012Applicant: International Business Machines CorporationInventors: Kathryn C. Fisher, Nicholas C. M. Fuller, Satyavolu S. Papa Rao, Xiaoyan Shao, Jeffrey Hedrick
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Publication number: 20110303274Abstract: The present disclosure provides a method of forming a back side surface field of a solar cell without utilizing screen printing. The method includes first forming a p-type dopant layer directly on the back side surface of the semiconductor substrate that includes a p/n junction utilizing an electrodeposition method. The p/n junction is defined as the interface that is formed between an n-type semiconductor portion of the substrate and an underlying p-type semiconductor portion of the substrate. The plated structure is then annealed to from a P++ back side surface field layer directly on the back side surface of the semiconductor substrate. Optionally, a metallic film can be electrodeposited on an exposed surface of the P++ back side surface layer.Type: ApplicationFiled: June 10, 2010Publication date: December 15, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kathryn C. Fisher, Nicholas C. M. Fuller, Satyavolu S. Papa Rao, Xiaoyan Shao, Jeffrey Hedrick
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Publication number: 20060264036Abstract: In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.Type: ApplicationFiled: July 24, 2006Publication date: November 23, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shyng-Tsong Chen, Stefanie Chiras, Matthew Colburn, Tomothy Dalton, Jeffrey Hedrick, Elbert Huang, Kaushik Kumar, Michael Lane, Kelly Malone, Chandrasekhar Narayan, Satyanarayana Nitta, Sampath Purushothaman, Robert Rosenberg, Christy Tyberg, Roy Yu
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Publication number: 20060197224Abstract: Structures having low-k multilayered dielectric diffusion barrier layer having at least one low-k sublayer and at least one air barrier sublayer are described herein. The multilayered dielectric diffusion barrier layer are diffusion barriers to metal and barriers to air permeation. Methods and compositions relating to the generation of the structures are also described. The advantages of utilizing these low-k multilayered dielectric diffusion barrier layer is a gain in chip performance through a reduction in capacitance between conducting metal features and an increase in reliability as the multilayered dielectric diffusion barrier layer are impermeable to air and prevent metal diffusion.Type: ApplicationFiled: May 2, 2006Publication date: September 7, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jeffrey Hedrick, Elbert Huang
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Publication number: 20050233597Abstract: A method for forming a self aligned pattern on an existing pattern on a substrate comprising applying a coating of a solution containing a masking material in a carrier, the masking material having an affinity for portions of the existing pattern; and allowing at least a portion of the masking material to preferentially assemble to the portions of the existing pattern. The pattern may be comprised of a first set of regions of the substrate having a first atomic composition and a second set of regions of the substrate having a second atomic composition different from the first composition. The first set of regions may include one or more metal elements and the second set of regions may include a dielectric. The first and second regions may be treated to have different surface properties. Structures made in accordance with the method. Compositions useful for practicing the method.Type: ApplicationFiled: June 2, 2005Publication date: October 20, 2005Inventors: Matthew Colburn, Stephen Gates, Jeffrey Hedrick, Elbert Huang, Satyanarayana Nitta, Sampath Purushothaman, Muthumanickam Sankarapandian
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Publication number: 20050206004Abstract: The present invention comprises an interconnect structure including a metal, interlayer dielectric and a ceramic diffusion barrier formed therebetween, where the ceramic diffusion barrier has a composition SivNwCxOyHz, where 0.1?v?0.9, 0?w?0.5, 0.01?x?0.9, 0?y?0.7, 0.01?z?0.8 for v+w+x+y+z=1. The ceramic diffusion barrier acts as a diffusion barrier to metals, i.e., copper. The present invention also comprises a method for forming the inventive ceramic diffusion barrier including the steps depositing a polymeric preceramic having a composition SivNwCxOyHz, where 0.1<v<0.8, 0<w<0.8, 0.05<x<0.8, 0<y<0.3, 0.05<z<0.8 for v+w+x+y+z=1 and then converting the polymeric preceramic layer into a ceramic diffusion barrier by thermal methods.Type: ApplicationFiled: May 13, 2005Publication date: September 22, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephan Cohen, Stephen Gates, Jeffrey Hedrick, Elbert Huang, Dirk Pfeiffer
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Publication number: 20050155574Abstract: A method is disclosed for ensuring operation of a motorized throttle. The presence of an obstruction, such as ice, is detected inside the motorized throttle. The obstruction is then removed within a predetermined time to free the motorized throttle. A new closed throttle position is then recorded as a zero degree reference from which to control a throttle plate to a desired angle.Type: ApplicationFiled: January 16, 2004Publication date: July 21, 2005Inventors: Jeffrey Hedrick, Ross Pursifull, Chang Yang
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Publication number: 20050127514Abstract: In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.Type: ApplicationFiled: December 8, 2003Publication date: June 16, 2005Inventors: Shyng-Tsong Chen, Stefanie Chiras, Matthew Colburn, Timothy Dalton, Jeffrey Hedrick, Elbert Huang, Kaushik Kumar, Michael Lane, Kelly Malone, Chandrasekhar Narayan, Satyanarayana Nitta, Sampath Purushothaman, Robert Rosenberg, Christy Tyberg, Roy Yu
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Process for removing impurities from low dielectric constant films disposed on semiconductor devices
Publication number: 20050087490Abstract: A process of removing impurities from a cured low dielectric constant organic polymeric film disposed on a semiconductor device. The process involves disposing a low dielectric constant curable organic polymeric film on an electrically conductive surface of a semiconductor device. The organic polymeric film is cured on the semiconductor device and thereupon contacted with supercritical carbon dioxide, optionally in the presence of at least one cosolvent.Type: ApplicationFiled: October 28, 2003Publication date: April 28, 2005Applicant: International Business Machines CorporationInventors: Mark Chace, Jeffrey Hedrick, Habib Hichri, Keith Pope, Jia Lee, Kelly Malone, Kenneth McCullough, Wayne Moreau, Darryl Restaino, Shahab Siddiqui -
Publication number: 20050087876Abstract: The present invention comprises an interconnect structure including a metal, interlayer dielectric and a ceramic diffusion barrier formed therebetween, where the ceramic diffusion barrier has a composition SivNwCxOyHz, where 0.1?v?0.9, 0?w?0.5, 0.01?x?0.9, 0?y?0.7, 0.01?z?0.8 for v+w+x+y+z=1. The ceramic diffusion barrier acts as a diffusion barrier to metals, i.e., copper. The present invention also comprises a method for forming the inventive ceramic diffusion barrier including the steps depositing a polymeric preceramic having a composition SivNwCxOyHz, where 0.1<v<0.8, 0<w<0.8, 0.05<x<0.8, 0<y<0.3, 0.05<z<0.8 for v+w+x+y+z=1 and then converting the polymeric preceramic layer into a ceramic diffusion barrier by thermal methods.Type: ApplicationFiled: July 25, 2003Publication date: April 28, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephan Cohen, Stephen Gates, Jeffrey Hedrick, Elbert Huang, Dirk Pfeiffer
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Publication number: 20050037604Abstract: A novel air-gap-containing interconnect wiring structure is described incorporating a solid low-k dielectric in the via levels, and a composite solid plus air-gap dielectric in the wiring levels. Also provided is a method for forming such an interconnect structure. The method is readily scalable to interconnect structures containing multiple wiring levels, and is compatible with Dual Damascene Back End of the Line (BEOL) processing.Type: ApplicationFiled: September 24, 2004Publication date: February 17, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Katherina Babich, Roy Carruthers, Timothy Dalton, Alfred Grill, Jeffrey Hedrick, Christopher Jahnes, Ebony Mays, Laurent Perraud, Sampath Purushothaman, Katherine Saenger
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Publication number: 20050008959Abstract: The present invention comprises a method for forming a hardmask including the steps of depositing a polymeric preceramic precursor film atop a substrate; converting the polymeric preceramic precursor film into at least one ceramic layer, where the ceramic layer has a composition of SivNwCxOyHz where 0.1?v?0.9, 0?w?0.5, 0.05?x?0.9, 0?y?0.5, 0.05?z?0.8 for v+w+x+y+z=1; forming a patterned photoresist atop the ceramic layer; patterning the ceramic layer to expose regions of the underlying substrate, where a remaining region of the underlying substrate is protected by the patterned ceramic layer; and etching the exposed region of the underlying substrate. Another aspect of the present invention is a buried etch stop layer having a composition of SivNwCxOyHz where 0.05<v<0.8, 0<w<0.9, 0.05<x<0.8, 0<y<0.8, 0.05<z<0.8 for v+w+x+y+z=1.Type: ApplicationFiled: August 10, 2004Publication date: January 13, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen Gates, Jeffrey Hedrick, Elbert Huang, Dirk Pfeiffer