Abstract: A transistor device includes a lightly doped layer of semiconductor material of a first type and a body region of semiconductor material of a second type. A source region of the first type is formed in the body region, the source region being more doped than the lightly doped layer. A drain region of the first type is formed in the lightly doped layer, the drain region being more doped than the lightly doped layer. A drift region of the lightly doped layer is further provided disposed between the body region and the drain region. Additionally, a gate electrode is provided surrounding the drain region. The gate electrode is partially disposed over a thin oxide and partially over a thick oxide, wherein the gate electrode extended over the thick oxide from the thin oxide controls the electric field in the drift region to increase the avalanche breakdown of the drain region.

Abstract: A transistor device is provided, including a lightly doped layer of semiconductor material of a first type and a body region of semiconductor material of a second type. A source region of the first type is formed in the body region. The source region being more doped than the lightly doped layer. A drain region of the first type is formed in the lightly doped layer, the drain region being more doped than the lightly doped layer. A drift region of the lightly doped layer is further provided disposed between the body region and the drain region. Additionally, a gate electrode is provided surrounding the drain region. The gate electrode is partially disposed over a thin oxide and partially over a thick oxide, wherein the gate electrode extended over the thick oxide from the thin oxide controls the electric field in the drift region to increase the avalanche breakdown of the drain region.

Abstract: A high bit rate Huffman decoder is provided for compressed data bit stream. In an exemplary embodiment, JPEG and MPEG data compression is explained. An oversized input data register receives sequential input data words to be decoded. Each new data word is appended to data already in the register by right shifting the new data word by the number of valid data bits in the register. A bitwise logical OR operation is performed to load an operative data register. The operative data register is left-shifted based upon the number of bits in a previous Huffman code word-coefficient pair. The left-most pair of the appropriate size is separated for examination. The separated bit strings are examined as representing the coefficient of the previous code word-coefficient pair and the current code word. The code word is used to access a Huffman lookup table. The lookup table provides the zeroes run length, coefficient size, and code word-coefficient pair length which is used for the next left shift.

Abstract: An integrated circuit process, voltage and temperature fluctuation self-aligning internal delay line circuit and method of operation. A PVT related reference signal is compared to a set of reference signals generated from a system voltage. A delay line is varied based upon the comparison results, generating a delayed timing signal related to PVT fluctuations.