Patents by Inventor Jeffrey A. Kessenich
Jeffrey A. Kessenich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10665307Abstract: Memory devices include an array of memory cells and circuitry for control and/or access of the array of memory cells, wherein the circuitry is configured to perform a method including applying a first voltage to the access line following a verify of the program operation then electrically floating the access line, connecting the access line to the first input of the operational amplifier, applying a second voltage to a second access line adjacent the access line, applying a reference current to the access line while applying the second voltage to the second access line, applying the reference voltage to the second input of the operational amplifier while applying the second voltage to the second access line, and indicating a fail status of the program operation if current flow to or from the access line exceeds the reference current sinking current from, or sourcing current to, respectively, the first access line.Type: GrantFiled: June 5, 2019Date of Patent: May 26, 2020Assignee: Micron Technology, Inc.Inventors: Jeffrey A. Kessenich, Joemar Sinipete, Chiming Chu, Jason L. Nevill, Kenneth W. Marr, Renato C. Padilla
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Publication number: 20190287634Abstract: Memory devices include an array of memory cells and circuitry for control and/or access of the array of memory cells, wherein the circuitry is configured to perform a method including applying a first voltage to the access line following a verify of the program operation then electrically floating the access line, connecting the access line to the first input of the operational amplifier, applying a second voltage to a second access line adjacent the access line, applying a reference current to the access line while applying the second voltage to the second access line, applying the reference voltage to the second input of the operational amplifier while applying the second voltage to the second access line, and indicating a fail status of the program operation if current flow to or from the access line exceeds the reference current sinking current from, or sourcing current to, respectively, the first access line.Type: ApplicationFiled: June 5, 2019Publication date: September 19, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Jeffrey A. Kessenich, Joemar Sinipete, Chiming Chu, Jason L. Nevill, Kenneth W. Marr, Renato C. Padilla
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Patent number: 10366767Abstract: Memory devices include an array of memory cells and circuitry for control and/or access of the array of memory cells, wherein the circuitry is configured to perform a method including applying a particular voltage to an unselected access line of a program operation, sensing a current of a selected access line of the program operation while applying the particular voltage to the unselected access line, indicating a fail status of the program operation if an absolute value of the sensed current of the selected access line is greater than a particular current, and proceeding with the program operation if the absolute value of the sensed current of the selected access line is less than a particular current.Type: GrantFiled: August 25, 2017Date of Patent: July 30, 2019Assignee: Micron Technology, Inc.Inventors: Jeffrey A. Kessenich, Joemar Sinipete, Chiming Chu, Jason L. Nevill, Kenneth W. Marr, Renato C. Padilla
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Publication number: 20170352431Abstract: Memory devices include an array of memory cells and circuitry for control and/or access of the array of memory cells, wherein the circuitry is configured to perform a method including applying a particular voltage to an unselected access line of a program operation, sensing a current of a selected access line of the program operation while applying the particular voltage to the unselected access line, indicating a fail status of the program operation if an absolute value of the sensed current of the selected access line is greater than a particular current, and proceeding with the program operation if the absolute value of the sensed current of the selected access line is less than a particular current.Type: ApplicationFiled: August 25, 2017Publication date: December 7, 2017Applicant: MICRON TECHNOLOGY, INC.Inventors: Jeffrey A. Kessenich, Joemar Sinipete, Chiming Chu, Jason L. Nevill, Kenneth W. Marr, Renato C. Padilla
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Patent number: 9281078Abstract: Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power consumption characteristics. Such methods might include applying a program pulse to a selected access line coupled to a memory cell selected for programming, verifying whether the selected memory cell has reached a desired data state, bringing the selected access line to a first voltage, applying a second voltage to an unselected access line, applying a reference current to the selected access line, and determining if a current flow between the selected access line and the unselected access line is greater than the reference current.Type: GrantFiled: June 12, 2014Date of Patent: March 8, 2016Assignee: Micron Technology, Inc.Inventors: Jeffrey A. Kessenich, Joemar Sinipete, Chiming Chu, Jason L. Nevill, Kenneth W. Marr, Renato C. Padilla
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Publication number: 20150364213Abstract: Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power consumption characteristics. Such methods might include applying a program pulse to a selected access line coupled to a memory cell selected for programming, verifying whether the selected memory cell has reached a desired data state, bringing the selected access line to a first voltage, applying a second voltage to an unselected access line, applying a reference current to the selected access line, and determining if a current flow between the selected access line and the unselected access line is greater than the reference current.Type: ApplicationFiled: June 12, 2014Publication date: December 17, 2015Applicant: Micron Technology, Inc.Inventors: Jeffrey A. Kessenich, Joemar Sinipete, Chiming Chu, Jason L. Nevill, Kenneth W. Marr, Renato C. Padilla
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Patent number: 7952936Abstract: Methods and devices are disclosed, some such methods comprising applying a verify pass-through voltage to unselected select lines of the floating-gate memory array that is greater than a read pass-through voltage applied to the unselected select lines. Other methods involve utilizing a cell current for reading a value from one or more memory cells in program-verify operations that is lower than a cell current for reading the value from the one or more memory cells in read operations.Type: GrantFiled: October 27, 2009Date of Patent: May 31, 2011Assignee: Micron Technology, Inc.Inventors: Andrei Mihnea, Todd Marquart, Jeffrey Kessenich
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Publication number: 20100046303Abstract: Methods and devices are disclosed, some such methods comprising applying a verify pass-through voltage to unselected select lines of the floating-gate memory array that is greater than a read pass-through voltage applied to the unselected select lines. Other methods involve utilizing a cell current for reading a value from one or more memory cells in program-verify operations that is lower than a cell current for reading the value from the one or more memory cells in read operations.Type: ApplicationFiled: October 27, 2009Publication date: February 25, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Andrei Mihnea, Todd Marquart, Jeffrey Kessenich
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Patent number: 7619931Abstract: Methods and devices are disclosed, such methods comprising applying a verify pass-through voltage to unselected select lines of the floating-gate memory array that is greater than a read pass-through voltage applied to the unselected select lines. Other methods involve utilizing a cell current for reading a value from one or more memory cells in program-verify operations that is lower than a cell current for reading value from one or more memory cells in read operations.Type: GrantFiled: June 26, 2007Date of Patent: November 17, 2009Assignee: Micron Technology, Inc.Inventors: Andrei Mihnea, Todd Marquart, Jeffrey Kessenich
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Publication number: 20090003078Abstract: Methods and devices are disclosed, such methods comprising applying a verify pass-through voltage to unselected select lines of the floating-gate memory array that is greater than a read pass-through voltage applied to the unselected select lines. Other methods involve utilizing a cell current for reading a value from one or more memory cells in program-verify operations that is lower than a cell current for reading value from one or more memory cells in read operations.Type: ApplicationFiled: June 26, 2007Publication date: January 1, 2009Inventors: Andrei Mihnea, Todd Marquart, Jeffrey Kessenich
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Publication number: 20070014158Abstract: A selected word line that is coupled to a cell to be programmed is biased during a program operation. The unselected word lines are biased with a negative potential to reduce the cell leakage at programming bit line potential. A programming pulse is applied to the bit line coupled to the cell to be programmed. During verification, the unselected word lines are biased back to ground potential.Type: ApplicationFiled: September 18, 2006Publication date: January 18, 2007Inventor: Jeffrey Kessenich
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Publication number: 20060146611Abstract: A selected wordline that is coupled to a cell to be programmed is biased during a program operation. The unselected wordlines are biased with a negative potential to reduce the cell leakage at programming bitline potential. A programming pulse is applied to the bitline coupled to the cell to be programmed. During verification, the unselected wordlines are biased back to ground potential.Type: ApplicationFiled: March 3, 2006Publication date: July 6, 2006Inventor: Jeffrey Kessenich
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Publication number: 20050248990Abstract: A selected wordline that is coupled to a cell to be programmed is biased during a program operation. The unselected wordlines are biased with a negative potential to reduce the cell leakage at programming bitline potential. A programming pulse is applied to the bitline coupled to the cell to be programmed. During verification, the unselected wordlines are biased back to ground potential.Type: ApplicationFiled: May 7, 2004Publication date: November 10, 2005Inventor: Jeffrey Kessenich
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Patent number: 6493280Abstract: A method of erasing memory cells in a flash memory device that recombines holes trapped in the tunnel oxide (after an erase operation) with electrons passing through the tunnel oxide is disclosed. The method uses an erase operation that over-erases all memory cells undergoing the erase operation. A cell healing operation is performed on the over-erased cells. The healing operation causes electrons to pass through the tunnel oxide and recombine with trapped holes. The recombination substantially reduces the trapped holes within the tunnel oxide without reducing the speed of the erase operation. Moreover, by reducing trapped holes, charge retention, overall performance and endurance of the flash memory cells are substantially increased.Type: GrantFiled: October 22, 2001Date of Patent: December 10, 2002Assignee: Micron Technology, Inc.Inventors: Andrei Mihnea, Jeffrey Kessenich, Chun Chen
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Publication number: 20020121653Abstract: A method of erasing memory cells in a flash memory device that recombines holes trapped in the tunnel oxide (after an erase operation) with electrons passing through the tunnel oxide is disclosed. The method uses an erase operation that over-erases all memory cells undergoing the erase operation. A cell healing operation is performed on the over-erased cells. The healing operation causes electrons to pass through the tunnel oxide and recombine with trapped holes. The recombination substantially reduces the trapped holes within the tunnel oxide without reducing the speed of the erase operation. Moreover, by reducing trapped holes, charge retention, overall performance and endurance of the flash memory cells are substantially increased.Type: ApplicationFiled: October 22, 2001Publication date: September 5, 2002Inventors: Andrei Mihnea, Jeffrey Kessenich, Chun Chen
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Patent number: 6426898Abstract: A method of erasing memory cells in a flash memory device that recombines holes trapped in the tunnel oxide (after an erase operation) with electrons passing through the tunnel oxide is disclosed. The method uses an erase operation that over-erases all memory cells undergoing the erase operation. A cell healing operation is performed on the over-erased cells. The healing operation causes electrons to pass through the tunnel oxide and recombine with trapped holes. The recombination substantially reduces the trapped holes within the tunnel oxide without reducing the speed of the erase operation. Moreover, by reducing trapped holes, charge retention, overall performance and endurance of the flash memory cells are substantially increased.Type: GrantFiled: March 5, 2001Date of Patent: July 30, 2002Assignee: Micron Technology, Inc.Inventors: Andrei Mihnea, Jeffrey Kessenich, Chun Chen