Abstract: A filter cartridge is provided having a filter element including media preferably constructed from continuous, reinforced, geometrically symmetrical, microporous membranes having three distinct pore zones. Preferred filter elements are assembled with high and/or increased filtration area to yield increased throughput cartridge elements. Preferred filter elements are constructed from reinforced microporous membranes that include a scrim having two sides at least substantially encapsulated within a first dope and at least one additional dope coated onto each side of the encapsulated scrim prior to the first dope being quenched.

Abstract: A method for retrieving excess pharmaceutical process fluid from the hold-up volume of a primary fluid filtration device. The hold-up volume is the volume of excess process fluid which accumulates in the bottom of the filter housing below the outlet opening thereof. Because it is considered valuable, the excess pharmaceutical process fluid is retrieved from the lower housing (22) via a drainage port (23) formed therein below the level of the outlet. The excess process fluid is then filtered in a supplemental filtration device (100) that is connected to the drainage port. The supplemental filtration device has a smaller volumetric capacity than the capacity of the primary fluid filtration device.

Abstract: A fluid filtration device is disclosed which includes a capsule housing having an upper housing portion defining an axial fluid inlet and a lower housing portion defining an axial fluid outlet, a filter assembly including an elongated mounting post and a plurality of filtration cells supported on the mounting post in axially spaced apart relationship, and structure operatively associated with the mounting post and the lower housing portion for effectuating axial compression of the filtration cells relative to the mounting post when the mounting post is engaged in the lower housing portion during assembly.

Abstract: A massively multiplexed central processing unit ("CPU") which has a plurality of independent computational circuits, a separate internal result bus for transmitting the resultant output from each of these computational circuits, and a plurality of general purpose registers coupled to each of the computational circuits. Each of the general purpose registers have multiplexed input ports which are connected to each of the result buses. Each of the general purpose registers also have an output port which is connected to a multiplexed input port of at least one of the computational circuits. Each of the computational circuits are dedicated to at least one unique mathematical function, and at least one of the computational circuits include at least one logical function. At least one of the computational circuits includes a plurality of concurrently operable mathematical and logical processing circuits, and an output multiplexer for selecting one of the resultant outputs for transmission on its result bus.