Patents by Inventor Jeffrey A. Magee

Jeffrey A. Magee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8090929
    Abstract: A digital system and method of operating the same. The system comprises a processor chip including a first elastic interface domain, wherein the first elastic interface domain comprises a first processor X logic and a first processor Y logic, wherein the first processor X and Y logic comprise first X and Y latches, respectively; and a first ASIC chip electrically coupled to the processor chip, wherein the first processor X and Y logics are configured to be simultaneously in a functional mode, wherein the first processor X logic is configured to switch from the functional mode to a scanning mode while the first processor Y logic remains in the functional mode, and wherein in response to the first processor Y logic being in the functional mode, the first processor Y logic is configured to generate a first reference ASIC clock signal to the first ASIC chip.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: January 3, 2012
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey A. Magee, Timothy Gerard McNamara, Walter Niklaus, Scott Barnett Swaney, Tobias Webel
  • Patent number: 7734944
    Abstract: A double data rate launch system and method in which the two-to-one multiplexer select signal delay is programmable and can be adjusted individually for each system. This allows the amount of delay to be minimized based on the actual set up time required, not the worst-case set-up time. The select signal to the multiplexer is delayed sufficiently to compensate for non-uniformity of duty cycle of data at the inputs to the multiplexer. Compensation of the non-uniformity allows the data on the wire to have a uniform duty cycle for all data transferred regardless of which latch is sourcing the data. The multiplexer that selects data from the two latches which are launching data on the edge of different clocks has a select line that is delayed by a variable amount to tune the select such that the data is clean at the input to the multiplexer on all ports.
    Type: Grant
    Filed: June 27, 2006
    Date of Patent: June 8, 2010
    Assignee: International Business Machines Corporation
    Inventors: Jonathan Y. Chen, Jeffrey A. Magee, David A. Webber
  • Publication number: 20090217000
    Abstract: A digital system and method of operating the same. The system comprises a processor chip including a first elastic interface domain, wherein the first elastic interface domain comprises a first processor X logic and a first processor Y logic, wherein the first processor X and Y logic comprise first X and Y latches, respectively; and a first ASIC chip electrically coupled to the processor chip, wherein the first processor X and Y logics are configured to be simultaneously in a functional mode, wherein the first processor X logic is configured to switch from the functional mode to a scanning mode while the first processor Y logic remains in the functional mode, and wherein in response to the first processor Y logic being in the functional mode, the first processor Y logic is configured to generate a first reference ASIC clock signal to the first ASIC chip.
    Type: Application
    Filed: September 24, 2008
    Publication date: August 27, 2009
    Inventors: Jeffrey A. Magee, Timothy Gerard McNamara, Walter Niklaus, Scott Barnett Swaney, Tobias Webel
  • Publication number: 20070300098
    Abstract: A double data rate launch system and method in which the two-to-one multiplexer select signal delay is programmable and can be adjusted individually for each system. This allows the amount of delay to be minimized based on the actual set up time required, not the worst-case set-up time. The select signal to the multiplexer is delayed sufficiently to compensate for non-uniformity of duty cycle of data at the inputs to the multiplexer. Compensation of the non-uniformity allows the data on the wire to have a uniform duty cycle for all data transferred regardless of which latch is sourcing the data. The multiplexer that selects data from the two latches which are launching data on the edge of different clocks has a select line that is delayed by a variable amount to tune the select such that the data is clean at the input to the multiplexer on all ports.
    Type: Application
    Filed: June 27, 2006
    Publication date: December 27, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan Y. Chen, Jeffrey A. Magee, David A. Webber
  • Publication number: 20040230813
    Abstract: Cryptographic functions are implemented in execution unit hardware on the CPU of a computer system. This implementation enables a lower latency for calling and executing cryptographic operations and increases the efficiency. This decreased latency greatly enhances the capability of general purpose processors in systems that frequently do many cryptographic operations, particularly when only small amounts of data are involved. This allows an implementation that can significantly accelerate the processes involved in doing secure online transactions.
    Type: Application
    Filed: May 12, 2003
    Publication date: November 18, 2004
    Applicant: International Business Machines Corporation
    Inventors: Mark A. Check, Jeffrey A. Magee, Timothy J. Slegel, Charles F. Webb