Abstract: One embodiment of this invention pertains to an OLED display that includes: multiple row lines and multiple column lines where the multiple row lines intersect the multiple column lines. The display also includes multiple elements and the multiple elements are at the intersections of the multiple row lines and the multiple column lines and are coupled to the multiple row lines and the multiple column lines. The display further includes a control unit that is coupled to the multiple row lines and the multiple column lines. The control unit selects one of the row lines and also selects for activation one or more of the multiple elements that are coupled to the selected row line by selecting one or more of the multiple column lines that are coupled to the one or more of the multiple elements that are to be activated. During a horizontal scanning period, the one or more nonselected row lines are floated and the zero or more nonselected column lines are floated.

Abstract: Control circuitry for an array of light emitting devices includes a first column line connected to each light emitting device in a column of light emitting devices. First column circuitry includes a first current source and a second current source. The first current source is connected to the first column line. The second current source is connected to the first column line. When a first light emitting device from the column of light emitting devices is to be turned on, the first current source is turned on until a voltage on the first column line is equal to a predetermined voltage. Then the first current source is turned off and the second current source supplies current sufficient to cause the first light emitting device to emit light to a first brightness level.

Abstract: A switched capacitor gain stage (110, 120) having a programmable gain factor. This gain factor is determined by the connection of desired gain determining components (14-17; 25-28) contained within a component array (100, 101). A sample and hold circuit (46) is provided for the storage of the error voltage of the entire gain-integrator stage. This stored error voltage (V.sub.error) is inverted and integrated one time for each integration of the input voltage (V.sub.in), thus eliminating the effects of the inherent offset voltages of the circuit from the output voltage (V.sub.out).

Abstract: A digital to analog converter (100) utilizes a current mirror connected to a reference voltage (V.sub.REF) to generate a constant reference current (I.sub.REF). A voltage divider (R.sub.1 and R.sub.2) is used in conjunction with a plurality of MOS transistors (X.sub.1 -X.sub.N) serving as current mirrors having specific current carrying capabilities which are controlled by selected binary digits (bits) of a digital signal. By the appropriate connection of desired ones of said plurality of MOS transistors, a specific fraction of said reference current is caused to flow through said plurality of MOS transistors. The amount of current flowing through said plurality of MOS transistors generates an output voltage (V.sub.OUT) from the digital to analog converter of this invention. This output voltage may be positive or negative with respect to the reference voltage, thus the output voltage is bipolar.